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ql-qlf: k6n10f: add tests for RAM with asymmetric port widths
Signed-off-by: Paweł Czarnecki <[email protected]>
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‎ql-qlf-plugin/tests/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -54,7 +54,9 @@ POST_SYNTH_SIM_TESTS = \
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qlf_k6n10f/bram_tdp_split \
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qlf_k6n10f/bram_sdp_split \
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qlf_k6n10f/dsp_mult_post_synth_sim \
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qlf_k6n10f/dsp_simd_post_synth_sim
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qlf_k6n10f/dsp_simd_post_synth_sim \
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qlf_k6n10f/bram_asymmetric_wider_write \
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qlf_k6n10f/bram_asymmetric_wider_read
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include $(shell pwd)/../../Makefile_test.common
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‎ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl‎

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yosys -import
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if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf }
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yosys -import ;
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read_verilog $::env(DESIGN_TOP).v
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design -save bram_tdp
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select spram_16x2048_32x1024
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select *
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synth_quicklogic -family qlf_k6n10f -top spram_16x2048_32x1024
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opt_expr -undriven
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opt_clean
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stat
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write_verilog sim/spram_16x2048_32x1024_post_synth.v
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select -assert-count 1 t:TDP36K
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select -clear
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design -load bram_tdp
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select spram_8x4096_16x2048
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select *
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synth_quicklogic -family qlf_k6n10f -top spram_8x4096_16x2048
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opt_expr -undriven
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opt_clean
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stat
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write_verilog sim/spram_8x4096_16x2048_post_synth.v
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select -assert-count 1 t:TDP36K
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select -clear
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design -load bram_tdp
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select spram_8x2048_16x1024
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select *
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synth_quicklogic -family qlf_k6n10f -top spram_8x2048_16x1024
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opt_expr -undriven
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opt_clean
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stat
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write_verilog sim/spram_8x2048_16x1024_post_synth.v
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select -assert-count 1 t:TDP36K
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select -clear
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design -load bram_tdp
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select spram_8x4096_32x1024
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select *
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synth_quicklogic -family qlf_k6n10f -top spram_8x4096_32x1024
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opt_expr -undriven
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opt_clean
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stat
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write_verilog sim/spram_8x4096_32x1024_post_synth.v
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select -assert-count 1 t:TDP36K
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‎ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.v‎

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// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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module spram_16x2048_32x1024 (
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clk,
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rce,
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ra,
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rq,
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wce,
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wa,
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wd
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);
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input clk;
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input rce;
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input [9:0] ra;
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output reg [31:0] rq;
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input wce;
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input [10:0] wa;
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input [15:0] wd;
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reg [31:0] memory [0:1023];
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always @(posedge clk) begin
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if (rce)
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rq <= memory[ra];
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if (wce)
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memory[wa / 2][(wa % 2) * 16+:16] <= wd;
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end
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integer i;
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initial for (i = 0; i < 1024; i = i + 1)
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memory[i] = 0;
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endmodule
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module spram_8x2048_16x1024 (
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clk,
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rce,
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ra,
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rq,
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wce,
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wa,
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wd
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);
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input clk;
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input rce;
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input [9:0] ra;
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output reg [15:0] rq;
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input wce;
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input [10:0] wa;
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input [7:0] wd;
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reg [15:0] memory [0:1023];
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always @(posedge clk) begin
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if (rce)
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rq <= memory[ra];
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if (wce)
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memory[wa / 2][(wa % 2) * 8+:8] <= wd;
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end
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integer i;
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initial for (i = 0; i < 1024; i = i + 1)
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memory[i] = 0;
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endmodule
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module spram_8x4096_16x2048 (
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clk,
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rce,
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ra,
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rq,
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wce,
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wa,
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wd
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);
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input clk;
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input rce;
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input [10:0] ra;
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output reg [15:0] rq;
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input wce;
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input [11:0] wa;
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input [7:0] wd;
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reg [15:0] memory [0:2047];
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always @(posedge clk) begin
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if (rce)
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rq <= memory[ra];
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if (wce)
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memory[wa / 2][(wa % 2) * 8+:8] <= wd;
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end
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integer i;
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initial for (i = 0; i < 2048; i = i + 1)
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memory[i] = 0;
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endmodule
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module spram_8x4096_32x1024 (
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clk,
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rce,
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ra,
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rq,
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wce,
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wa,
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wd
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);
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input clk;
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input rce;
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input [9:0] ra;
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output reg [31:0] rq;
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input wce;
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input [11:0] wa;
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input [7:0] wd;
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reg [31:0] memory [0:1023];
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always @(posedge clk) begin
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if (rce)
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rq <= memory[ra];
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if (wce)
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memory[wa / 4][(wa % 4) * 8+:8] <= wd;
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end
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integer i;
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initial for (i = 0; i < 1024; i = i + 1)
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memory[i] = 0;
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endmodule

‎ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/sim/Makefile‎

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# Copyright 2020-2022 F4PGA Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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TESTBENCH = bram_asymmetric_wider_read_tb.v
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POST_SYNTH = spram_16x2048_32x1024_post_synth spram_8x4096_16x2048_post_synth spram_8x2048_16x1024_post_synth spram_8x4096_32x1024_post_synth
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READ_ADDR_WIDTH = 10 11 10 10
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WRITE_ADDR_WIDTH = 11 12 11 12
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READ_DATA_WIDTH = 32 16 16 32
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WRITE_DATA_WIDTH = 16 8 8 8
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TOP = spram_16x2048_32x1024 spram_8x4096_16x2048 spram_8x2048_16x1024 spram_8x4096_32x1024
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READ_ADDR_DEFINES = $(foreach awidth, $(READ_ADDR_WIDTH),-DREAD_ADDR_WIDTH="$(awidth)")
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WRITE_ADDR_DEFINES = $(foreach awidth, $(WRITE_ADDR_WIDTH),-DWRITE_ADDR_WIDTH="$(awidth)")
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READ_DATA_DEFINES = $(foreach dwidth, $(READ_DATA_WIDTH),-DREAD_DATA_WIDTH="$(dwidth)")
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WRITE_DATA_DEFINES = $(foreach dwidth, $(WRITE_DATA_WIDTH),-DWRITE_DATA_WIDTH="$(dwidth)")
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TOP_DEFINES = $(foreach top, $(TOP),-DTOP="$(top)")
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VCD_DEFINES = $(foreach vcd, $(POST_SYNTH),-DVCD="$(vcd).vcd")
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SIM_LIBS = $(shell find ../../../../qlf_k6n10f -name "*.v" -not -name "*_map.v")
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define simulate_post_synth
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@iverilog -vvvv -g2005 $(word $(1),$(READ_ADDR_DEFINES)) $(word $(1),$(WRITE_ADDR_DEFINES)) $(word $(1),$(READ_DATA_DEFINES)) $(word $(1),$(WRITE_DATA_DEFINES)) $(word $(1),$(TOP_DEFINES)) $(word $(1),$(VCD_DEFINES)) -o $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).v $(SIM_LIBS) $(TESTBENCH) > $(word $(1),$(POST_SYNTH)).vvp.log 2>&1
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@vvp -vvvv $(word $(1),$(POST_SYNTH)).vvp > $(word $(1),$(POST_SYNTH)).vcd.log 2>&1
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endef
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define clean_post_synth_sim
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@rm -rf $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
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endef
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sim:
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$(call simulate_post_synth,1)
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$(call simulate_post_synth,2)
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$(call simulate_post_synth,3)
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$(call simulate_post_synth,4)

‎ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/sim/bram_asymmetric_wider_read_tb.v‎

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// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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`timescale 1ns/1ps
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`define STRINGIFY(x) `"x`"
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module TB;
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localparam PERIOD = 50;
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localparam ADDR_INCR = 1;
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reg clk;
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reg rce;
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reg [`READ_ADDR_WIDTH-1:0] ra;
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wire [`READ_DATA_WIDTH-1:0] rq;
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reg wce;
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reg [`WRITE_ADDR_WIDTH-1:0] wa;
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reg [`WRITE_DATA_WIDTH-1:0] wd;
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initial clk = 0;
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initial ra = 0;
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initial rce = 0;
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initial forever #(PERIOD / 2.0) clk = ~clk;
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initial begin
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$dumpfile(`STRINGIFY(`VCD));
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$dumpvars;
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end
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integer a;
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reg done;
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initial done = 1'b0;
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reg [`READ_DATA_WIDTH-1:0] expected;
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always @(posedge clk) begin
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case (`READ_DATA_WIDTH / `WRITE_DATA_WIDTH)
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1: expected <= (a | (a << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}};
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2: expected <= ((((2*a+1) | ((2*a+1) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) << `WRITE_DATA_WIDTH) |
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(((2*a) | ((2*a) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}});
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4: expected <= (((4*a) | ((4*a) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) |
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((((4*a+1) | ((4*a+1) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) << `WRITE_DATA_WIDTH) |
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((((4*a+2) | ((4*a+2) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) << (2 * `WRITE_DATA_WIDTH)) |
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((((4*a+3) | ((4*a+3) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) << (3 * `WRITE_DATA_WIDTH));
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default: expected <= ((a) | ((a) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}};
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endcase
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end
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wire error = ((a != 0) && read_test) ? rq !== expected : 0;
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integer error_cnt = 0;
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always @ (posedge clk)
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begin
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if (error)
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error_cnt <= error_cnt + 1'b1;
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end
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reg read_test;
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initial read_test = 0;
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initial #(1) begin
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// Write data
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for (a = 0; a < (1<<`WRITE_ADDR_WIDTH); a = a + ADDR_INCR) begin
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@(negedge clk) begin
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wa = a;
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wd = a | (a << 20) | 20'h55000;
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wce = 1;
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end
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@(posedge clk) begin
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#(PERIOD/10) wce = 0;
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end
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end
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// Read data
87+
read_test = 1;
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for (a = 0; a < (1<<`READ_ADDR_WIDTH); a = a + ADDR_INCR) begin
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@(negedge clk) begin
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ra = a;
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rce = 1;
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end
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@(posedge clk) begin
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#(PERIOD/10) rce = 0;
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if ( rq !== expected) begin
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$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected, a);
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end else begin
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$display("%d: OK: act=%x exp=%x at %x", $time, rq, expected, a);
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end
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end
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end
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done = 1'b1;
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end
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// Scan for simulation finish
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always @(posedge clk) begin
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if (done)
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$finish_and_return( (error_cnt == 0) ? 0 : -1 );
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end
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case (`STRINGIFY(`TOP))
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"spram_16x2048_32x1024": begin
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spram_16x2048_32x1024 #() simple (
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.clk(clk),
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.rce(rce),
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.ra(ra),
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.rq(rq),
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.wce(wce),
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.wa(wa),
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.wd(wd)
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);
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end
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"spram_8x4096_16x2048": begin
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spram_8x4096_16x2048 #() simple (
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.clk(clk),
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.rce(rce),
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.ra(ra),
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.rq(rq),
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.wce(wce),
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.wa(wa),
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.wd(wd)
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);
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end
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"spram_8x2048_16x1024": begin
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spram_8x2048_16x1024 #() simple (
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.clk(clk),
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.rce(rce),
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.ra(ra),
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.rq(rq),
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.wce(wce),
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.wa(wa),
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.wd(wd)
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);
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end
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"spram_8x4096_32x1024": begin
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spram_8x4096_32x1024 #() simple (
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.clk(clk),
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.rce(rce),
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.ra(ra),
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.rq(rq),
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.wce(wce),
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.wa(wa),
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.wd(wd)
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);
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end
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endcase
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endmodule

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