Skip to content

Commit 2110bf6

Browse files
chipsec-bbcidscott90
chipsec-bbci
authored and
dscott90
committed
Update to release/1.13.19
Signed-off-by: ChipSec <[email protected]>
1 parent e448af4 commit 2110bf6

File tree

388 files changed

+3786
-2375
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

388 files changed

+3786
-2375
lines changed

‎_sources/development/Developing.rst.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ Most modules read some platform configuration and then pass or fail based on the
1717

1818
.. code-block:: python
1919
20-
ble = self.cs.control.get_list_by_name('BiosLockEnable').is_all_value(1)
20+
ble = self.cs.control.get('BiosLockEnable')
2121
2222
3. React based on the status of the control:
2323

‎_sources/index.rst.txt‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
.. CHIPSEC 1.13.18 documentation file, created by
1+
.. CHIPSEC 1.13.19 documentation file, created by
22
sphinx-quickstart on Wed Mar 25 13:24:44 2015.
33
You can adapt this file completely to your liking, but it should at least
44
contain the root `toctree` directive.
55
6-
CHIPSEC 1.13.18
6+
CHIPSEC 1.13.19
77
===============
88

99
CHIPSEC is a framework for analyzing platform level security of

‎_sources/modules/chipsec.cfg.8086.adl.xml.rst.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ Path: chipsec\\cfg\\8086\\adl.xml
55

66

77
CHIPSEC: Platform Security Assessment Framework
8-
Copyright (c) 2023, Intel Corporation
8+
Copyright (c) 2021-2022, Intel Corporation
99

1010
This program is free software; you can redistribute it and/or
1111
modify it under the terms of the GNU General Public License

‎_sources/modules/chipsec.cfg.8086.apl.xml.rst.txt‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
apl
2+
=======
3+
4+
Path: chipsec\\cfg\\8086\\apl.xml
5+
6+
7+
XML configuration for Apollo Lake based SoCs
8+
document id 334818/334819
9+

‎_sources/modules/chipsec.cfg.8086.avn.xml.rst.txt‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
avn
2+
=======
3+
4+
Path: chipsec\\cfg\\8086\\avn.xml
5+
6+
7+
XML configuration for Avoton based platforms
8+
9+
* Intel(R) Atom(TM) Processor C2000 Product Family for Microserver, September 2014
10+
http://www.intel.com/content/www/us/en/processors/atom/atom-c2000-microserver-datasheet.html
11+

‎_sources/modules/chipsec.cfg.8086.bdw.xml.rst.txt‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
bdw
2+
=======
3+
4+
Path: chipsec\\cfg\\8086\\bdw.xml
5+
6+
7+
XML configuration for Broadwell based platforms
8+

‎_sources/modules/chipsec.cfg.8086.bdx.xml.rst.txt‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
bdx
2+
=======
3+
4+
Path: chipsec\\cfg\\8086\\bdx.xml
5+
6+
7+
XML configuration file for Broadwell Server based platforms
8+
Intel (c) Xeon Processor E5 v4 Product Family datasheet Vol. 2
9+
Intel (c) Xeon Processor E7 v4 Product Family datasheet Vol. 2
10+
Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
11+
Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
12+
Intel (c) C610 Series Chipset and Intel (c) X99 Chipset Platform Controller Hub (PCH) datasheet
13+

‎_sources/modules/chipsec.cfg.8086.byt.xml.rst.txt‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
byt
2+
=======
3+
4+
Path: chipsec\\cfg\\8086\\byt.xml
5+
6+
7+
XML configuration for Bay Trail based platforms
8+
9+
* Intel(R) Atom(TM) Processor E3800 Product Family Datasheet, May 2016, Revision 4.0
10+
http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html
11+

‎_sources/modules/chipsec.cfg.8086.cfl.xml.rst.txt‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
cfl
2+
=======
3+
4+
Path: chipsec\\cfg\\8086\\cfl.xml
5+
6+
7+
XML configuration file for Coffee Lake
8+
9+
* 8th Generation Intel(R) Processor Family for S-Processor Platforms
10+
https://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
11+

‎_sources/modules/chipsec.cfg.8086.cht.xml.rst.txt‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
cht
2+
=======
3+
4+
Path: chipsec\\cfg\\8086\\cht.xml
5+
6+
7+
XML configuration for Cherry Trail and Braswell SoCs
8+
9+
* Intel(R) Atom(TM) Processor Z8000 series datasheet
10+
http://www.intel.com/content/www/us/en/processors/atom/atom-z8000-datasheet-vol-2.html
11+
12+
* N-series Intel(R) Pentium(R) and Celeron(R) Processors Datasheet
13+
http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-celeron-n-series-datasheet-vol-2.pdf
14+

0 commit comments

Comments
 (0)