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x86 asm: move rotation and bit instructoins in from x86-assembly-cheat
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‎README.adoc

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* link:userland/arch/x86_64/or.S[OR]
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* link:userland/arch/x86_64/xor.S[XOR]
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=== x86 shift and rotate instructions
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<<intel-manual-1>> 5.1.5 "Shift and Rotate Instructions"
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* link:userland/arch/x86_64/shl.S[SHL and SHR]
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SHift left or Right and insert 0.
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CF == the bit that got shifted out.
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Application: quick unsigned multiply and divide by powers of 2.
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* link:userland/arch/x86_64/sal.S[SAL and SAR]
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Application: signed multiply and divide by powers of 2.
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Mnemonics: Shift Arithmetic Left and Right
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Keeps the same sign on right shift.
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Not directly exposed in C, for which signed shift is undetermined behavior, but does exist in Java via the `>>>` operator. C compilers can omit it however.
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SHL and SAL are exactly the same and have the same encoding: https://stackoverflow.com/questions/8373415/difference-between-shl-and-sal-in-80x86/56621271#56621271
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* link:userland/arch/x86_64/rol.S[ROL and ROR]
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Rotates the bit that is going out around to the other side.
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* link:userland/arch/x86_64/rol.S[RCL and RCR]
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Like ROL and ROR, but insert the carry bit instead, which effectively generates a rotation of 8 + 1 bits. TODO application.
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=== x86 bit and byte instructions
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<<intel-manual-1>> 5.1.6 "Bit and Byte Instructions"
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* link:userland/arch/x86_64/bt.S[BT]
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Bit test: test if the Nth bit a bit of a register is set and store the result in the CF FLAG.
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....
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CF = reg[N]
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....
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* link:userland/arch/x86_64/btr.S[BTR]
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Do a BT and then set the bit to 0.
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* link:userland/arch/x86_64/btc.S[BTC]
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Do a BT and then swap the value of the tested bit.
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* link:userland/arch/x86_64/setcc.S[SETcc]
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Set a a byte of a register to 0 or 1 depending on the cc condition.
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* link:userland/arch/x86_64/test.S[TEST]
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Like <<x86-binary-arithmetic-instructions,CMP>> but does AND instead of SUB:
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....
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ZF = (!(X && Y)) ? 1 : 0
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....
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=== x86 control transfer instructions
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<<intel-manual-1>> 5.1.7 "Control Transfer Instructions"

‎userland/arch/x86_64/bt.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-bit-and-byte-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* 0101 1010 */
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mov $0x5A, %r12
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bt $0, %r12w
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LKMC_ASSERT(jnc)
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bt $1, %r12w
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LKMC_ASSERT(jc)
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bt $2, %r12w
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LKMC_ASSERT(jnc)
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bt $3, %r12w
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LKMC_ASSERT(jc)
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bt $4, %r12w
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LKMC_ASSERT(jc)
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bt $5, %r12w
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LKMC_ASSERT(jnc)
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bt $6, %r12w
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LKMC_ASSERT(jc)
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bt $7, %r12w
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LKMC_ASSERT(jnc)
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/* The register is unchanged. */
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LKMC_ASSERT_EQ(%r12, $0x5A)
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#if 0
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/* There is no Byte decoding for bt:
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* Error: operand size mismatch for `bt'
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*/
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bt $0, %r12b
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#endif
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LKMC_EPILOGUE

‎userland/arch/x86_64/btc.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-bit-and-byte-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* 0101 1010 */
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mov $0x5A, %r12
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btc $0, %r12
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LKMC_ASSERT(jnc)
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LKMC_ASSERT_EQ(%r12, $0x5B)
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/* 0101 1010 */
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btc $0, %r12
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LKMC_ASSERT(jc)
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LKMC_ASSERT_EQ(%r12, $0x5A)
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LKMC_EPILOGUE

‎userland/arch/x86_64/btr.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-bit-and-byte-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* 0101 1010 */
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mov $0x5A, %r12
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btr $1, %r12
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LKMC_ASSERT(jc)
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LKMC_ASSERT_EQ(%r12, $0x58)
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/* 0101 1000 */
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btr $1, %r12
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LKMC_ASSERT(jnc)
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LKMC_ASSERT_EQ(%r12, $0x58)
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LKMC_EPILOGUE

‎userland/arch/x86_64/rcl.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-shift-and-rotate-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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mov $0x81, %r12
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clc
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rcl $1, %r12b
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/* We'll have to save and restore flags across our asserts!
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* 2x PUSHF to maintain 16-bit stack alignment.
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* https://github.com/cirosantilli/linux-kernel-module-cheat#x86_64-calling-convention
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*/
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pushf
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pushf
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LKMC_ASSERT(jc)
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LKMC_ASSERT_EQ(%r12, $2)
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popf
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rcl $1, %r12b
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pushf
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LKMC_ASSERT(jnc)
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LKMC_ASSERT_EQ(%r12, $5)
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popf
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rcr $2, %r12b
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pushf
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LKMC_ASSERT(jnc)
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LKMC_ASSERT_EQ(%r12, $0x81)
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popf
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rcr $1, %r12b
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pushf
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LKMC_ASSERT(jc)
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LKMC_ASSERT_EQ(%r12, $0x40)
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add $16, %rsp
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LKMC_EPILOGUE

‎userland/arch/x86_64/rol.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-shift-and-rotate-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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mov $0x81, %r12
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/* axl = 03h, CF = 1 */
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rol $1, %r12b
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LKMC_ASSERT(jc)
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LKMC_ASSERT_EQ(%r12, $3)
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/* axl = 04h, CF = 0 */
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rol $1, %r12b
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LKMC_ASSERT(jnc)
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LKMC_ASSERT_EQ(%r12, $6)
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/* axl = 03h, CF = 0 */
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ror $2, %r12b
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LKMC_ASSERT(jc)
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LKMC_ASSERT_EQ(%r12, $0x81)
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/* axl = 81h, CF = 1 */
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ror $1, %r12b
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LKMC_ASSERT(jc)
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LKMC_ASSERT_EQ(%r12, $0x0C0)
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LKMC_EPILOGUE

‎userland/arch/x86_64/sal.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-shift-and-rotate-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* 0xFF == -1 in 2's complement with 8-bits. */
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mov $0xFF, %r12
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sal %r12b
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LKMC_ASSERT(jc)
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/* 0xFE == -2 in 2's complement with 8-bits. */
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LKMC_ASSERT_EQ(%r12, $0xFE)
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/* SAR*/
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sar %r12b
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LKMC_ASSERT(jnc)
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/* -1 */
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LKMC_ASSERT_EQ(%r12, $0xFF)
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/* SAR rounds to -infinity: -1 goes to -1 again. */
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sar %r12b
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LKMC_ASSERT(jc)
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/* -1 */
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LKMC_ASSERT_EQ(%r12, $0xFF)
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LKMC_EPILOGUE

‎userland/arch/x86_64/setcc.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-bit-and-byte-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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mov $0xFF, %r12
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/* Set Carry flag. */
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stc
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/* Check for carry flag. */
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setc %r12b
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/* Carry flag was set, so set the r12b to 1. */
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LKMC_ASSERT_EQ(%r12, $1)
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/* Clear carry flag. */
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clc
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setc %r12b
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LKMC_ASSERT_EQ(%r12, $0)
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#if 0
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/* The operand size can only be one byte:
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* Error: operand size mismatch for `setc'
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*/
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setc %eax
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#endif
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LKMC_EPILOGUE

‎userland/arch/x86_64/shl.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-shift-and-rotate-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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mov $0x81, %r12
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/* Shift left by one. */
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shl %r12b
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LKMC_ASSERT(jc)
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LKMC_ASSERT_EQ(%r12, $2)
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/* Shift left by one. */
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shl %r12b
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LKMC_ASSERT(jnc)
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LKMC_ASSERT_EQ(%r12, $4)
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/* Shift right by one. */
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shr %r12b
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LKMC_ASSERT(jnc)
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LKMC_ASSERT_EQ(%r12, $2)
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/* Shift left by 2 immediate.
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* Differentent coding than shift by 1.
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*/
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shl $2, %r12b
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LKMC_ASSERT(jnc)
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LKMC_ASSERT_EQ(%r12, $8)
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/* Shift left by 2 in cl register. */
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mov $2, %cl
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shl %cl, %r12b
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LKMC_ASSERT(jnc)
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LKMC_ASSERT_EQ(%r12, $0x20)
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#if 0
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/* cl is the only possible register choice
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* Error: operand type mismatch for `shr'
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*/
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shr %bl, %ax
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#endif
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LKMC_EPILOGUE

‎userland/arch/x86_64/test.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-bit-and-byte-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* 0xF0 & 0x00 == 0x00 */
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mov $0xF0, %r12
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test $0, %r12b
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/* The comparison was equal 0. */
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LKMC_ASSERT(jz)
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/* r12 is unchanged. */
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LKMC_ASSERT_EQ(%r12, $0x0F0)
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/* 0xF0 & 0x18 == 0x10 != 0x00 */
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mov $0xF0, %r12
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test $0x18, %r12b
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LKMC_ASSERT(jnz)
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LKMC_ASSERT_EQ(%r12, $0x0F0)
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/* test %rax, %rax vs cmp $0, %rax: test produces a shorter
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* encoding to decide if a register equals zero or not.
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* http://stackoverflow.com/questions/147173/x86-assembly-testl-eax-against-eax
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*/
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LKMC_EPILOGUE

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