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baremetal: arm multicore attempt
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README.adoc

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shows ARM version up to `armv6`, so maybe `armv6` is not implemented?
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=== ARM exception level
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=== ARM baremetal
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In this section we will focus on learning ARM architecture concepts that can only learnt on baremetal setups.
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Userland information can be found at: https://github.com/cirosantilli/arm-assembly-cheat
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==== ARM exception level
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ARM exception levels are analogous to x86 <<ring0,rings>>.
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3
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....
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==== ARM multicore
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TODO get working: CPU1 not waking up:
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....
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./run --arch aarch64 --baremetal arch/aarch64/no_bootloader/multicore
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....
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Source: link:baremetal/arch/aarch64/no_bootloader/multicore.S[]
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CPU 0 of this program enters a spinlock loop: it repeatedly checks if a given memory address is `1`.
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So, we need CPU 1 to come to the rescue to that memory address be `1`, otherwise CPU 0 will be stuck there forever.
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Bibliography:
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* https://stackoverflow.com/questions/20055754/arm-start-wakeup-bringup-the-other-cpu-cores-aps-and-pass-execution-start-addre
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* https://stackoverflow.com/questions/980999/what-does-multicore-assembly-language-look-like/33651438#33651438
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=== How we got some baremetal stuff to work
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It is nice when thing just work.
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/* https://github.com/cirosantilli/linux-kernel-module-cheat#arm-multicore */
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.global mystart
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mystart:
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/* Reset spinlock. */
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mov x0, #0
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ldr x1, =spinlock
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str x0, [x1]
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/* Read cpu id into x1. */
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mrs x1, mpidr_el1
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and x1, x1, #3
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cbz x1, 1f
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/* Only CPU 1 reaches this point and sets the spinlock. */
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mov x0, #1
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ldr x1, =spinlock
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str x0, [x1]
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b .
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1:
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/* Only CPU 0 reaches this point. */
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ldr x0, spinlock
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cbz x0, 1b
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/* Semihost exit. */
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mov x1, #0x26
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movk x1, #2, lsl #16
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str x1, [sp,#0]
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mov x0, #0
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str x0, [sp,#8]
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mov x1, sp
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mov w0, #0x18
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hlt 0xf000
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spinlock:
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.skip 8

baremetal/arch/aarch64/no_bootloader/semihost_exit.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#semihosting */
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.global mystart
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mystart:
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mov x1, #0x26

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