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cirosantillicirosantilli
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x86 asm: move most data transfer instructions from x86-assembly-cheat
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‎README.adoc

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@@ -12361,6 +12361,102 @@ Bibliography:
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* <<intel-manual-1>> 3.7.5 "Specifying an Offset"
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* https://sourceware.org/binutils/docs-2.18/as/i386_002dMemory.html
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=== x86 data transfer instructions
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5.1.1 "Data Transfer Instructions"
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* link:userland/arch/x86_64/lea.S[]: LEA
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* Integer typecasts
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** link:userland/arch/x86_64/movzx.S[]: MOVZX
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** link:userland/arch/x86_64/movsx.S[]: MOVSX
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==== x86 CQTO and CLTQ instructions
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Examples:
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* link:userland/arch/x86_64/cqto.S[] CQTO
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* link:userland/arch/x86_64/cltq.S[] CLTQ
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Instructions without E suffix: sign extend RAX into RDX:RAX.
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Instructions E suffix: sign extend withing RAX itself.
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Common combo with idiv 32-bit, which takes the input from `edx:eax`: so you need to set up `edx` before calling it.
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Has some Intel vs AT&T name overload hell:
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* https://stackoverflow.com/questions/17170388/trying-to-understand-the-assembly-instruction-cltd-on-x86/50315201#50315201
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* https://sourceware.org/binutils/docs/as/i386_002dMnemonics.html
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GNU GAS accepts both syntaxes:
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[options="header"]
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|===
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|Intel |AT&T |From |To
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|CBW
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|CBTW
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|AL
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|AX
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|CWDE
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|CWTL
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|AX
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|EAX
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|CWD
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|CWTD
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|AX
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|DX:AX
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|CDQ
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|CLTD
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|EAX
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|EDX:EAX
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|CDQE
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|CLTQ
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|EAX
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|RAX
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|CQO
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|CQTO
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|RAX
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|RDX:RAX
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|===
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==== x86 CMOVcc instructions
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* link:userland/arch/x86_64/cmovcc.S[]: CMOVcc
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mov if a condition is met:
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....
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CMOVcc a, b
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....
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Equals:
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....
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if(flag) a = b
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....
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where `cc` are the same flags as Jcc.
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Vs jmp:
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* http://stackoverflow.com/questions/14131096/why-is-a-conditional-move-not-vulnerable-for-branch-prediction-failure
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* http://stackoverflow.com/questions/27136961/what-is-it-about-cmov-which-improves-cpu-pipeline-performance
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* http://stackoverflow.com/questions/26154488/difference-between-conditional-instructions-cmov-and-jump-instructions
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* http://stackoverflow.com/questions/6754454/speed-difference-between-if-else-and-ternary-operator-in-c?lq=1#comment8007791_6754495
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Not necessarily faster because of branch prediction.
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This is partly why the ternary `?` C operator exists: http://stackoverflow.com/questions/3565368/ternary-operator-vs-if-else
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It is interesting to compare this with ARMv7 conditional executaion: which is available for all instructions: <<arm-conditional-execution>>
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=== x86 binary arithmetic instructions
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<<intel-manual-1>> 5.1.2 "Binary Arithmetic Instructions":

‎userland/arch/x86_64/cltq.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-cqto-and-cltq-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* CLTQ: top bit is zero: extend with zeroes. */
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mov $0x123456787FFFFFFF, %rax
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cltq
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LKMC_ASSERT_EQ(%rax, $0x000000007FFFFFFF)
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/* CLTQ: top bit is one: extend with ones. */
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mov $0x1234567880000000, %rax
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cltq
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LKMC_ASSERT_EQ(%rax, $0xFFFFFFFF80000000)
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/* CWTL: zeroes top 32-bits. */
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mov $0x123456789ABC8EF0, %rax
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cwtl
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LKMC_ASSERT_EQ(%rax, $0xFFFF8EF0)
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CWTL
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/* CBTW. */
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mov $0x123456789ABCDE80, %rax
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cbtw
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LKMC_ASSERT_EQ(%rax, $0x123456789ABCFF80)
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CWTL
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LKMC_EPILOGUE

‎userland/arch/x86_64/cmovcc.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-cmovcc-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* Carry flag clear. */
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clc
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mov $0, %rax
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mov $1, %rbx
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/* Don't move: carry flag not set. */
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cmovc %rbx, %rax
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LKMC_ASSERT_EQ(%rax, $0)
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/* Carry flag clear. */
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clc
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mov $0, %rax
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mov $1, %rbx
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/* Move because checking NC. */
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cmovnc %rbx, %rax
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LKMC_ASSERT_EQ(%rax, $1)
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/* Carry flag set. */
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stc
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mov $0, %rax
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mov $1, %rbx
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/* Move. */
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cmovc %rbx, %rax
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LKMC_ASSERT_EQ(%rax, $1)
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#if 0
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/* Immediates not supported:
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* Error: operand type mismatch for `cmovc' */
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cmovc $1, %rax
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#endif
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LKMC_EPILOGUE

‎userland/arch/x86_64/cqto.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-cqto-and-cltq-instructions */
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* Quad to Octo: top bit is zero: extend with zeroes. */
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mov $0x7FFFFFFFFFFFFFFF, %rax
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mov $0x123456789ABCDEF0, %rdx
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cqto
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mov %rax, %r12
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mov %rdx, %r13
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/* rax is unchanged. */
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LKMC_ASSERT_EQ(%r12, $0x7FFFFFFFFFFFFFFF)
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/* rdx is filled with zeros. */
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LKMC_ASSERT_EQ(%r13, $0)
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/* Quad to Octo: top bit is one: extend with ones. */
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mov $0x8000000000000000, %rax
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mov $0x123456789ABCDEF0, %rdx
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cqto
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mov %rax, %r12
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mov %rdx, %r13
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LKMC_ASSERT_EQ(%r12, $0x8000000000000000)
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LKMC_ASSERT_EQ(%r13, $0xFFFFFFFFFFFFFFFF)
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/* Intel equivalent syntax also accepte by GNU GAS. */
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mov $0x7FFFFFFFFFFFFFFF, %rax
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mov $0x123456789ABCDEF0, %rdx
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cqo
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mov %rax, %r12
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mov %rdx, %r13
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LKMC_ASSERT_EQ(%r12, $0x7FFFFFFFFFFFFFFF)
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LKMC_ASSERT_EQ(%r13, $0)
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/* Smaller size example: Double to Quad.
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* Also zeroes top 32-bits of RDX like many 32 to 64 operaions. */
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mov $0xFFFFFFFF7FFFFFFF, %rax
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mov $0x123456789ABCDEF0, %rdx
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cltd
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mov %rax, %r12
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mov %rdx, %r13
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LKMC_ASSERT_EQ(%r12, $0xFFFFFFFF7FFFFFFF)
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LKMC_ASSERT_EQ(%r13, $0)
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/* Even smaller size example: Word to Doubleword.
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* Unlike the 32-bit one, does not zero out the top 32-bits of RDX. */
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mov $0xFFFFFFFFFFFF7FFF, %rax
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mov $0x123456789ABCDEF0, %rdx
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cwtd
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mov %rax, %r12
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mov %rdx, %r13
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LKMC_ASSERT_EQ(%r12, $0xFFFFFFFFFFFF7FFF)
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LKMC_ASSERT_EQ(%r13, $0x123456789ABC0000)
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LKMC_EPILOGUE

‎userland/arch/x86_64/lea.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-data-transfer-instructions
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*
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* Load Effective Address.
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*
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* Like MOV, but load the address instead of the value.
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*
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* Useful in particular for RIP relative addressing.
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*/
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* RIP relative addressing. */
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lea my_label(%rip), %rax
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LKMC_ASSERT_EQ(%rax, $my_label)
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/* Also supports the usual addressing operations. */
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mov $my_label, %rax
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mov $2, %rbx
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lea 4(%rax,%rbx,2), %rdx
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LKMC_ASSERT_EQ(%rdx, $my_label_2)
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LKMC_EPILOGUE
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my_label: .skip 8
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my_label_2:

‎userland/arch/x86_64/movsx.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-data-transfer-instructions
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*
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* LIke MOVZX but sign extend.
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*/
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* Top bit is 0, extend with zero. */
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mov $0x1234567F, %eax
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movsx %al, %ax
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LKMC_ASSERT_EQ_32(%eax, $0x1234007F)
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/* Top bit is 1: extend with one. */
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mov $0x12345680, %eax
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movsx %al, %ax
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LKMC_ASSERT_EQ_32(%eax, $0x1234FF80)
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LKMC_EPILOGUE

‎userland/arch/x86_64/movzx.S

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/* https://github.com/cirosantilli/linux-kernel-module-cheat#x86-data-transfer-instructions
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*
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* mov and zero extend
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*
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* unsigned typecast to larger types in 2's complement.
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*
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* MOV does this automatically from 32 to 64 bits:
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* https://stackoverflow.com/questions/11177137/why-do-x86-64-instructions-on-32-bit-registers-zero-the-upper-part-of-the-full-6
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*/
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#include <lkmc.h>
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LKMC_PROLOGUE
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/* Top bit is 0, extend with zero. */
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mov $0x1234567F, %eax
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movzx %al, %ax
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LKMC_ASSERT_EQ_32(%eax, $0x1234007F)
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/* Top bit is 1: does not matter, stil zero extends. */
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mov $0x1234568F, %eax
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movzx %al, %ax
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LKMC_ASSERT_EQ_32(%eax, $0x1234008F)
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#if 0
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/* must be a register, otherwise x86 cannot know how to size it:
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* Error: unsupported syntax for `movzx' */
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movzx $0, %eax
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/* Operands have the same size. Fist must be larger.
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* Error: unsupported syntax for `movzx' */
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movzx %al, %al
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#endif
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LKMC_EPILOGUE

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