@@ -2247,12 +2247,12 @@ module Impl<FullStateConfigSig Config> {
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Typ getTyp ( DataFlowType t ) { result = t }
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bindingset [ tc, t, tail]
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- Ap apCons ( TypedContent tc , Typ t , Ap tail ) { result .getHead ( ) = tc and exists ( t ) and exists ( tail ) }
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+ Ap apCons ( TypedContent tc , Typ t , Ap tail ) { result .getHead ( ) = tc . getContent ( ) and exists ( t ) and exists ( tail ) }
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class ApHeadContent = Content ;
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pragma [ noinline]
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- ApHeadContent getHeadContent ( Ap ap ) { result = ap .getHead ( ) . getContent ( ) }
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+ ApHeadContent getHeadContent ( Ap ap ) { result = ap .getHead ( ) }
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ApHeadContent projectToHeadContent ( Content c ) { result = c }
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@@ -2313,15 +2313,15 @@ module Impl<FullStateConfigSig Config> {
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}
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pragma [ nomagic]
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- private predicate clear ( NodeEx node , Ap ap ) { clearContent ( node , ap .getHead ( ) . getContent ( ) ) }
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+ private predicate clear ( NodeEx node , Ap ap ) { clearContent ( node , ap .getHead ( ) ) }
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pragma [ nomagic]
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private predicate expectsContentCand ( NodeEx node , Ap ap ) {
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exists ( Content c |
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PrevStage:: revFlow ( node ) and
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PrevStage:: readStepCand ( _, c , _) and
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expectsContentEx ( node , c ) and
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- c = ap .getHead ( ) . getContent ( )
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+ c = ap .getHead ( )
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)
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}
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@@ -2372,9 +2372,9 @@ module Impl<FullStateConfigSig Config> {
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tails = strictcount ( DataFlowType t , AccessPathFront apf | Stage4:: consCand ( tc , t , apf ) ) and
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nodes =
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strictcount ( NodeEx n , FlowState state |
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- Stage4:: revFlow ( n , state , any ( AccessPathFrontHead apf | apf .getHead ( ) = tc ) )
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+ Stage4:: revFlow ( n , state , any ( AccessPathFrontHead apf | apf .getHead ( ) = tc . getContent ( ) ) )
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or
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- flowCandSummaryCtx ( n , state , any ( AccessPathFrontHead apf | apf .getHead ( ) = tc ) )
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+ flowCandSummaryCtx ( n , state , any ( AccessPathFrontHead apf | apf .getHead ( ) = tc . getContent ( ) ) )
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) and
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accessPathApproxCostLimits ( apLimit , tupleLimit ) and
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apLimit < tails and
@@ -2390,7 +2390,7 @@ module Impl<FullStateConfigSig Config> {
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not expensiveLen2unfolding ( tc )
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} or
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TConsCons ( TypedContent tc1 , DataFlowType t , TypedContent tc2 , int len ) {
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- Stage4:: consCand ( tc1 , t , TFrontHead ( tc2 ) ) and
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+ Stage4:: consCand ( tc1 , t , TFrontHead ( tc2 . getContent ( ) ) ) and
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len in [ 2 .. accessPathLimit ( ) ] and
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not expensiveLen2unfolding ( tc1 )
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} or
@@ -2448,7 +2448,7 @@ module Impl<FullStateConfigSig Config> {
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override int len ( ) { result = 1 }
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- override AccessPathFront getFront ( ) { result = TFrontHead ( tc ) }
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+ override AccessPathFront getFront ( ) { result = TFrontHead ( tc . getContent ( ) ) }
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override predicate isCons ( TypedContent head , DataFlowType typ , AccessPathApprox tail ) { head = tc and typ = t and tail = TNil ( ) }
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}
@@ -2471,7 +2471,7 @@ module Impl<FullStateConfigSig Config> {
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override int len ( ) { result = len }
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- override AccessPathFront getFront ( ) { result = TFrontHead ( tc1 ) }
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+ override AccessPathFront getFront ( ) { result = TFrontHead ( tc1 . getContent ( ) ) }
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override predicate isCons ( TypedContent head , DataFlowType typ , AccessPathApprox tail ) {
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head = tc1 and
@@ -2503,12 +2503,12 @@ module Impl<FullStateConfigSig Config> {
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override int len ( ) { result = len }
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- override AccessPathFront getFront ( ) { result = TFrontHead ( tc ) }
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+ override AccessPathFront getFront ( ) { result = TFrontHead ( tc . getContent ( ) ) }
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override predicate isCons ( TypedContent head , DataFlowType typ , AccessPathApprox tail ) {
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head = tc and
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(
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- exists ( TypedContent tc2 | Stage4:: consCand ( tc , typ , TFrontHead ( tc2 ) ) |
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+ exists ( TypedContent tc2 | Stage4:: consCand ( tc , typ , TFrontHead ( tc2 . getContent ( ) ) ) |
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tail = TConsCons ( tc2 , _, _, len - 1 )
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or
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len = 2 and
@@ -2884,7 +2884,7 @@ module Impl<FullStateConfigSig Config> {
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head = head_ and typ = t and tail = tail_
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}
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- override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head_ ) }
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+ override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head_ . getContent ( ) ) }
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pragma [ assume_small_delta]
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override AccessPathApproxCons getApprox ( ) {
@@ -2949,7 +2949,7 @@ module Impl<FullStateConfigSig Config> {
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tail .length ( ) = len - 1
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}
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- override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head1 ) }
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+ override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head1 . getContent ( ) ) }
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override AccessPathApproxCons getApprox ( ) {
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result = TConsCons ( head1 , t , head2 , len ) or
@@ -2984,7 +2984,7 @@ module Impl<FullStateConfigSig Config> {
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Stage5:: consCand ( head_ , typ , tail .getApprox ( ) ) and tail .length ( ) = len - 1
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}
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- override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head_ ) }
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+ override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head_ . getContent ( ) ) }
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override AccessPathApproxCons getApprox ( ) { result = TCons1 ( head_ , len ) }
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