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Address review comments
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3 files changed

+20
-17
lines changed

3 files changed

+20
-17
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -6200,21 +6200,11 @@ SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
62006200
return SD;
62016201

62026202
// (umin (sub a, b) a) -> (usubo a, b); (select usubo.1, a, usubo.0)
6203-
//
6204-
// IR:
6205-
// %sub = sub %a, %b
6206-
// %cond = umin %sub, %a
6207-
// ->
6208-
// %usubo = usubo %a, %b
6209-
// %overflow = extractvalue %usubo, 1
6210-
// %sub = extractvalue %usubo, 0
6211-
// %cond = select %overflow, %a, %sub
62126203
if (N0.getOpcode() == ISD::SUB) {
6213-
SDValue A, B, C;
6214-
if (sd_match(N, m_UMin(m_Sub(m_Value(A), m_Value(B)), m_Value(C)))) {
6215-
EVT AVT = A.getValueType();
6216-
if (A == C && TLI.isOperationLegalOrCustom(ISD::USUBO, AVT)) {
6217-
SDVTList VTs = DAG.getVTList(AVT, MVT::i1);
6204+
SDValue A, B;
6205+
if (sd_match(N, m_UMin(m_Sub(m_Value(A), m_Value(B)), m_Deferred(A)))) {
6206+
if (TLI.isOperationLegalOrCustom(ISD::USUBO, VT)) {
6207+
SDVTList VTs = DAG.getVTList(VT, MVT::i1);
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SDValue USO = DAG.getNode(ISD::USUBO, DL, VTs, A, B);
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return DAG.getSelect(DL, VT, USO.getValue(1), A, USO.getValue(0));
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}
Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
2+
3+
; GitHub issue #161036
4+
5+
define i64 @underflow_compare_fold(i64 %a, i64 %b) {
6+
; CHECK-LABEL: underflow_compare_fold
7+
; CHECK: // %bb.0:
8+
; CHECK-NEXT: subs x8, x0, x1
9+
; CHECK-NEXT: csel x0, x0, x8, lo
10+
; CHECK-NEXT: ret
11+
%sub = sub i64 %a, %b
12+
%cond = tail call i64 @llvm.umin.i64(i64 %sub, i64 %a)
13+
ret i64 %cond
14+
}

llvm/test/CodeGen/X86/underflow-compare-fold.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,14 +2,13 @@
22

33
; GitHub issue #161036
44

5-
define i64 @subIfNoUnderflow_umin(i64 %a, i64 %b) {
6-
; CHECK-LABEL: subIfNoUnderflow_umin
5+
define i64 @underflow_compare_fold(i64 %a, i64 %b) {
6+
; CHECK-LABEL: underflow_compare_fold
77
; CHECK-LABEL: %bb.0
88
; CHECK-NEXT: movq %rdi, %rax
99
; CHECK-NEXT: subq %rsi, %rax
1010
; CHECK-NEXT: cmovbq %rdi, %rax
1111
; CHECK-NEXT: retq
12-
entry:
1312
%sub = sub i64 %a, %b
1413
%cond = tail call i64 @llvm.umin.i64(i64 %sub, i64 %a)
1514
ret i64 %cond

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