Benches and toggle pin work on am6254

Author: ckormanyos

ref_app/src/app/benchmark/readme.md

@@ -78,44 +78,50 @@ $\pi$ using a Gauss AGM method with help
 from the [`decwide_t`](https://github.com/ckormanyos/real-time-cpp/blob/master/ref_app/src/math/wide_decimal/decwide_t.h)
 template class.
 
-A typical range of performance classes is shown in the following table.
+A very wide range of microcontroller performance classes is shown in the following table.
 The benchmark used is a ${\sim}100$ decimal digit AGM $\pi$ calculation.
 
 | Target             |  runtime $[ms]$ |  relative  |
 |--------------------|-----------------|------------|
-| `am335x`           |  1.5            |    1.0     |
-| `stm32f446`        |  5.1            |    3.4     |
-| `rpi_pico2_rp2350` |  6.3            |    4.2     |
-| `wch_ch32v307`     |  8.0            |    5.3     |
-| `xtensa_esp32_s3`  |  9.1            |    6.1     |
-| `rpi_pico_rp2040`  |  19             |    13      |
-| `avr`              |  420            |    280     |
+| `am6254_soc_`      |  0.37           |    1.0     |
+| `am335x`           |  1.5            |    4.0     |
+| `stm32f446`        |  5.1            |    14      |
+| `rpi_pico2_rp2350` |  6.3            |    17      |
+| `wch_ch32v307`     |  8.0            |    22      |
+| `xtensa_esp32_s3`  |  9.1            |    25      |
+| `rpi_pico_rp2040`  |  19             |    51      |
+| `avr`              |  420            |    760     |
 
 There are strikingly differing performance classes
 for the $8$-bit MICROCHIP(R) AVR controller of the ARDUINO
 and the $32$-bit ARM(R) 8 controller
 of the BeagleBone Black Edition, Rev. C.
 The $\pi$ calculation requires approximately
-$420~\text{ms}$ and $1.5~\text{ms}$,
+$420~\text{ms}$ and $1.5~\text{ms,}~$
 respectively, on these two microcontroller systems.
 
+The $64$-bit ARM(R)v8-a (i.e., Cortex(R) A53) performs the
+calculation (running on one single A53 core of the PocketBeagle2 board)
+in $0.37~\text{ms.}$
+
 The $32$-bit ARM(R) Cortex(R) M4F controller on
 the `stm32f446` board performs the calculation in
 the middle of the two extremes, with a result
 of $5.1~\text{ms}$.
 
 The $32$-bit RISC-V controller (having a novel _open-source_ core)
 on the `wch_ch32v307` board boasts a quite respectable
-time of $8.0~\text{ms}$.
+time of $8.0~\text{ms.}$
 
 Running on only one core (core0) of the $32$-bit
 controller of the `xtensa_esp32_s3` board results in
 a runtime of $9.1~\text{ms}$ for the calculation.
 
 Using only one core (core1) on the $32$-bit ARM(R) Cortex(R) M0+
 controller of the `rpi_pico_rp2040` board results in a calculation
-time of $19~\text{ms}$. The next generation `rpi_pico2_rp2350`
+time of $19~\text{ms.}~$
+The next generation `rpi_pico2_rp2350`
 with dual ARM(R) Cortex(R) M33 cores definitively improves on this
-(still using only core1) with a time of $6.3~\text{ms}$.
+(still using only core1) with a time of $6.3~\text{ms.}~$
 This is slightly more than $3~\text{ms}$ times faster
 than its predecessor.

ref_app/src/mcal/am6254_soc/mcal_benchmark.h

@@ -17,7 +17,7 @@
   {
     namespace benchmark
     {
-      typedef mcal::port::port_pin<mcal::reg::gpio0, 36U> benchmark_port_type;
+      using benchmark_port_type = mcal::port::port_pin<mcal::reg::gpio0, 36U>;
     }
   }
 

ref_app/src/mcal/am6254_soc/mcal_irq.h

@@ -8,6 +8,21 @@
 #ifndef MCAL_IRQ_2010_04_10_H
   #define MCAL_IRQ_2010_04_10_H
 
+  #include <core_macros.h>
+
+  #if defined(__cplusplus)
+  extern "C"
+  {
+  #endif
+
+  static inline void mcal_irq_enable_all(void);
+  static inline void mcal_irq_disable_all(void);
+
+  #if defined(__cplusplus)
+  }
+  #endif
+
+  #if defined(__cplusplus)
   namespace mcal
   {
     namespace irq
@@ -16,9 +31,22 @@
 
       void init(const config_type*);
 
-      inline void enable_all () { /* TBD enable/disable fiqs/irqs for this arch. */ }
-      inline void disable_all() { /* TBD enable/disable fiqs/irqs for this arch. */ }
+      inline void enable_all() { ::mcal_irq_enable_all(); }
+      inline void disable_all() { ::mcal_irq_disable_all(); }
     }
   }
+  #endif
+
+  #if defined(__cplusplus)
+  extern "C"
+  {
+  #endif
+
+  static inline void mcal_irq_enable_all(void) { arch_enable_ints(); arch_enable_fiqs(); }
+  static inline void mcal_irq_disable_all(void) { arch_disable_fiqs(); arch_disable_ints(); }
+
+  #if defined(__cplusplus)
+  }
+  #endif
 
 #endif // MCAL_IRQ_2010_04_10_H

ref_app/src/mcal/am6254_soc/mcal_port.cpp

@@ -9,4 +9,12 @@
 
 void mcal::port::init(const config_type*)
 {
+  // The pad configuration of gpio0.37 is on pad37 (empirical observation).
+  // So we must initialize pad37 since we will use gpio0.36 as the
+  // benchmark toggle-pin.
+  mcal::port::port_pin<mcal::reg::gpio0, 36U>::set_pin_low();
+  mcal::port::port_pin<mcal::reg::gpio0, 36U>::set_direction_output();
+
+  mcal::port::port_pin<mcal::reg::gpio0, 37U>::set_pin_low();
+  mcal::port::port_pin<mcal::reg::gpio0, 37U>::set_direction_output();
 }

ref_app/src/mcal/am6254_soc/mcal_port.h

@@ -92,8 +92,6 @@
             /* GPIO1 has no pad configuration */
           }
 
-          *reinterpret_cast<volatile std::uint32_t*>(static_cast<std::uintptr_t>(instance_base + static_cast<std::uintptr_t>((pin/32U) * UINT32_C(0x28)) + static_cast<std::uintptr_t>(UINT32_C(0x0C)) /* GPIO_CLR_DATA */)) |= static_cast<std::uint32_t>(UINT32_C(1) << pin_mod32);
-          *reinterpret_cast<volatile std::uint32_t*>(static_cast<std::uintptr_t>(instance_base + static_cast<std::uintptr_t>((pin/32U) * UINT32_C(0x28)) + static_cast<std::uintptr_t>(UINT32_C(0x04)) /* GPIO_OUT_DATA */)) &= static_cast<std::uint32_t>(~(static_cast<std::uint32_t>(UINT32_C(1) << pin_mod32)));
           *reinterpret_cast<volatile std::uint32_t*>(static_cast<std::uintptr_t>(instance_base + static_cast<std::uintptr_t>((pin/32U) * UINT32_C(0x28)) + static_cast<std::uintptr_t>(UINT32_C(0x00)) /* GPIO_DIR      */)) &= static_cast<std::uint32_t>(~(static_cast<std::uint32_t>(UINT32_C(1) << pin_mod32)));
         }
 

ref_app/target/micros/am6254_soc/Code/Appli/Core/a53/main.c

@@ -8,6 +8,7 @@
 #include <core_macros.h>
 #include <gic-500.h>
 #include <mcal_cpu.h>
+#include <mcal_irq.h>
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -26,6 +27,7 @@ extern ATTRIBUTE_USED int main(void);
 extern void main_core1(void);
 extern void main_core2(void);
 extern void main_core3(void);
+extern void main_core0_init(void);
 
 ATTRIBUTE_USED void timer_isr(void);
 ATTRIBUTE_USED void main_x(void);
@@ -38,7 +40,7 @@ void main_x(void)
   // Move the core initialization functions into main_init().
   main_init(ActiveCore);
 
-  if     (ActiveCore == UINT32_C(0)) { (void) main(); }
+  if     (ActiveCore == UINT32_C(0)) { main_core0_init(); (void) main(); }
   else if(ActiveCore == UINT32_C(1)) { main_core1(); }
   else if(ActiveCore == UINT32_C(2)) { main_core2(); }
   else if(ActiveCore == UINT32_C(3)) { main_core3(); }
@@ -88,8 +90,7 @@ static void main_init(const uint32_t ActiveCore)
   pGICR->CORE[ActiveCore].SGI_PPI.ICFGR0 &= ~(uint32_t)(1 << ((29 - 16) * 2)); // clear bit to set level-triggered
 
   /* enable global interrupt */
-  arch_enable_ints();
-  arch_enable_fiqs();
+  mcal_irq_enable_all();
 
   /* start the timer */
   ARM64_WRITE_SYSREG(CNTPS_TVAL_EL1, UINT64_C(0x0BEBC200));

ref_app/target/micros/am6254_soc/Code/Appli/Core/a53/main_cores.cpp

@@ -7,6 +7,9 @@
 
 #include <mcal_cpu.h>
 #include <mcal_led.h>
+#include <mcal_osc.h>
+#include <mcal_port.h>
+#include <mcal_wdg.h>
 
 #include <util/utility/util_time.h>
 
@@ -20,26 +23,30 @@ namespace local
 extern "C" auto main_core1(void) -> void;
 extern "C" auto main_core2(void) -> void;
 extern "C" auto main_core3(void) -> void;
+extern "C" auto main_core0_init(void) -> void;
 
 extern "C" auto main_core1(void) -> void { local::main_core_worker(mcal::led::led1()); }
 extern "C" auto main_core2(void) -> void { local::main_core_worker(mcal::led::led2()); }
 extern "C" auto main_core3(void) -> void { local::main_core_worker(mcal::led::led3()); }
 
+extern "C" auto main_core0_init(void) -> void
+{
+  mcal::wdg::init (nullptr);
+  mcal::port::init(nullptr);
+  mcal::osc::init (nullptr);
+}
+
 static auto local::main_core_worker(mcal::led::led_base& my_led) -> void
 {
   using local_timer_type = util::timer<std::uint64_t>;
   using local_tick_type = typename local_timer_type::tick_type;
 
-  local_timer_type led_timer(local_timer_type::seconds(local_tick_type { UINT8_C(1) }));
-
   my_led.toggle();
 
   for(;;)
   {
-    while(!led_timer.timeout()) { mcal::cpu::nop(); }
+    local_timer_type::blocking_delay(local_timer_type::seconds(local_tick_type { UINT8_C(1) }));
 
     my_led.toggle();
-
-    led_timer.start_interval(local_timer_type::seconds(local_tick_type { UINT8_C(1) }));
   }
 }

ref_app/target/micros/am6254_soc/Code/Startup/Core/a53/core_macros.h

@@ -1,72 +1,91 @@
-#ifndef _CORE_MACROS_H
-#define _CORE_MACROS_H
+#ifndef CORE_MACROS_2025_07_28_H
+  #define CORE_MACROS_2025_07_28_H
 
-#if defined(__GNUC__)
-#pragma GCC system_header
-#endif
+  #if defined(__GNUC__)
+  #pragma GCC system_header
+  #endif
 
-#include <stdint.h>
-#include <stdbool.h>
+  #if defined(__cplusplus)
 
-#define DSB __asm__ volatile("dsb sy" ::: "memory")
-#define ISB __asm__ volatile("isb" ::: "memory")
+  #include <cstdint>
 
-#define STRINGIFY(x) #x
-#define TOSTRING(x) STRINGIFY(x)
+  extern "C"
+  {
 
-#define ARM64_READ_SYSREG(reg) \
-({ \
+  #else
+
+  #include <stdint.h>
+  #include <stdbool.h>
+
+  #endif
+
+  #define DSB __asm__ volatile("dsb sy" ::: "memory")
+  #define ISB __asm__ volatile("isb" ::: "memory")
+
+  #define STRINGIFY(x) #x
+  #define TOSTRING(x) STRINGIFY(x)
+
+  #define ARM64_READ_SYSREG(reg) \
+  ({ \
     uint64_t _val; \
     __asm__ volatile("mrs %0," TOSTRING(reg) : "=r" (_val)); \
     _val; \
-})
+  })
 
-#define ARM64_WRITE_SYSREG(reg, val) \
-({ \
+  #define ARM64_WRITE_SYSREG(reg, val) \
+  ({ \
     __asm__ volatile("msr " TOSTRING(reg) ", %0" :: "r" (val)); \
     ISB; \
-})
+  })
 
-#define CF do { __asm__ volatile("" ::: "memory"); } while(0)
+  #define CF do { __asm__ volatile("" ::: "memory"); } while(0)
 
-static inline void arch_enable_ints(void) {
+  static inline void arch_enable_ints(void) 
+  {
     CF;
     __asm__ volatile("msr daifclr, #2" ::: "memory");
-}
+  }
 
-static inline void arch_disable_ints(void) {
+  static inline void arch_disable_ints(void)
+  {
     __asm__ volatile("msr daifset, #2" ::: "memory");
     CF;
-}
+  }
 
-static inline bool arch_ints_disabled(void) {
+  static inline bool arch_ints_disabled(void)
+  {
     unsigned long state;
 
     __asm__ volatile("mrs %0, daif" : "=r"(state));
     state &= (1<<7);
 
     return !!state;
-}
+  }
 
-static inline void arch_enable_fiqs(void) {
+  static inline void arch_enable_fiqs(void)
+  {
     CF;
     __asm__ volatile("msr daifclr, #1" ::: "memory");
-}
+  }
 
-static inline void arch_disable_fiqs(void) {
+  static inline void arch_disable_fiqs(void)
+  {
     __asm__ volatile("msr daifset, #1" ::: "memory");
     CF;
-}
+  }
 
-static inline bool arch_fiqs_disabled(void) {
+  static inline bool arch_fiqs_disabled(void)
+  {
     unsigned long state;
 
     __asm__ volatile("mrs %0, daif" : "=r"(state));
     state &= (1<<6);
 
     return !!state;
-}
-
+  }
 
+  #if defined(__cplusplus)
+  }
+  #endif
 
-#endif /*_CORE_MACROS_H*/
+#endif // CORE_MACROS_2025_07_28_H