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Commit 705d16e

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author
Timmy
committed
add dtrsm perf (clblas 2.7.1) on w9100 with 14502 driver
1 parent 8299035 commit 705d16e

4 files changed

+124
-0
lines changed

‎doc/performance/clBLAS_2.7.1/W9100/clblas271_w9100_dtrsm_col_left_lower_unit_14502.csv

Lines changed: 31 additions & 0 deletions
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1+
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‎doc/performance/clBLAS_2.7.1/W9100/clblas271_w9100_dtrsm_col_left_upper_unit_14502.csv

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
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‎doc/performance/clBLAS_2.7.1/W9100/clblas271_w9100_dtrsm_col_right_lower_unit_14502.csv

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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1+
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2+
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3+
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‎doc/performance/clBLAS_2.7.1/W9100/clblas271_w9100_dtrsm_col_right_upper_unit_14502.csv

Lines changed: 31 additions & 0 deletions
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@@ -0,0 +1,31 @@
1+
m,n,k,lda,ldb,ldc,offa,offb,offc,alpha,beta,order,transa,transb,side,uplo,diag,function,device,library,label,GFLOPS
2+
192,192,192,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,10.6716
3+
384,384,384,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,70.5926
4+
576,576,576,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,180.089
5+
768,768,768,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,285.734
6+
960,960,960,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,408.363
7+
1152,1152,1152,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,555.832
8+
1344,1344,1344,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,690.637
9+
1536,1536,1536,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,519.496
10+
1728,1728,1728,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,863.036
11+
1920,1920,1920,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,901.732
12+
2112,2112,2112,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1036.75
13+
2304,2304,2304,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1045.06
14+
2496,2496,2496,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1126.92
15+
2688,2688,2688,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1170.15
16+
2880,2880,2880,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1148.58
17+
3072,3072,3072,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,981.035
18+
3264,3264,3264,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1198.84
19+
3456,3456,3456,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1220.03
20+
3648,3648,3648,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1244.95
21+
3840,3840,3840,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1177.25
22+
4032,4032,4032,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1272.59
23+
4224,4224,4224,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1262.03
24+
4416,4416,4416,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1301.38
25+
4608,4608,4608,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1216.99
26+
4800,4800,4800,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1315.69
27+
4992,4992,4992,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1319.76
28+
5184,5184,5184,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1343.41
29+
5376,5376,5376,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1312.79
30+
5568,5568,5568,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1357.02
31+
5760,5760,5760,0,0,0,0,0,0,1.0,1.0,column,none,none,right,upper,unit,dtrsm,gpu,clblas,clblas271_w9100_dtrsm_col_right_upper_unit_14502,1348.39

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