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Fix incorrect I2C test
1 parent f6c05b9 commit 6261acf

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3 files changed

+69
-71
lines changed

3 files changed

+69
-71
lines changed

clash-cores/src/Clash/Cores/I2C/ByteMaster.hs

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,12 @@ data ByteStateMachine = Idle | Active | Start | Read | Write | Ack | Stop
1717
deriving (Show, Generic, NFDataX, Eq)
1818

1919
data I2COperation = ReadData | WriteData (BitVector 8)
20-
deriving (Generic, NFDataX)
20+
deriving (Generic, NFDataX, BitPack)
21+
2122
getWriteData :: I2COperation -> BitVector 8
2223
getWriteData ReadData = 0
2324
getWriteData (WriteData d) = d
25+
2426
data ByteMasterS
2527
= ByteS
2628
{ _srState :: ShiftRegister

clash-cores/test/Test/Cores/I2C.hs

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -20,10 +20,8 @@ system0 clk arst = bundle (registerFile,done,fault)
2020
(_dout,hostAck,_busy,al,ackOut,i2cO) =
2121
i2c clk arst rst (pure True) (pure 19) claim i2cOp (pure True) i2cI
2222

23-
i2cOp = mux claim (Just <$> mux write (WriteData <$> din) (pure ReadData)) (pure Nothing)
24-
25-
(claim,write,din,done,fault) = unbundle $
26-
config clk (bundle (rst, fmap not rst,hostAck,ackOut,al))
23+
(claim,i2cOp,done,fault) =
24+
unbundle $ config clk (bundle (rst,fmap not rst,hostAck,ackOut,al))
2725

2826
(sclOut,sdaOut) = unbundle i2cO
2927
scl = fmap (bitCoerce . isNothing) sclOut
@@ -46,7 +44,8 @@ systemResult :: (Vec 16 (Unsigned 8), Bool, Bool)
4644
systemResult = L.last (sampleN 200050 system)
4745

4846
i2cTest :: TestTree
49-
i2cTest = testCase "i2c core testcase passed."
50-
$ assertBool "i2c core test procedure failed" (not f)
47+
i2cTest = testCase "i2c core testcase passed"
48+
$ assertBool "i2c core test procedure failed" (not fault)
5149
where
52-
(_, _, f) = L.last $ takeWhile (\ (_, done, _) -> not done) $ sample system
50+
fault =
51+
any (\(_,_,f) -> f) (takeWhile (\ (_, done, _) -> not done) $ sample system)

clash-cores/test/Test/Cores/I2C/Config.hs

Lines changed: 60 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,9 @@ module Test.Cores.I2C.Config where
44

55
import Clash.Prelude
66
import Clash.Explicit.SimIO
7+
import Numeric (showHex)
8+
9+
import Clash.Cores.I2C.ByteMaster (I2COperation(..))
710

811
data ConfStateMachine = CONFena |
912
CONFaddr | CONFaddrAck |
@@ -12,24 +15,22 @@ data ConfStateMachine = CONFena |
1215
CONFstop
1316
deriving Show
1417

15-
data ConfS = ConfS { i2cConfStateM :: ConfStateMachine
16-
, i2cClaim :: Bool
17-
, i2cWrite :: Bool
18-
, i2cDin :: Vec 8 Bit
19-
, i2cLutIndex :: Index 16
20-
, i2cFault :: Bool
18+
data ConfS = ConfS { i2cConfStateM :: ConfStateMachine
19+
, i2cConfClaim :: Bool
20+
, i2cConfOp :: Maybe I2COperation
21+
, i2cConfLutIndex :: Index 16
22+
, i2cConfFault :: Bool
2123
}
2224

2325
type ConfI = (Bool,Bool,Bool,Bool,Bool)
24-
type ConfO = (Bool,Bool,BitVector 8,Bool,Bool)
26+
type ConfO = (Bool,Maybe I2COperation,Bool,Bool)
2527

2628
confInit :: ConfS
27-
confInit = ConfS { i2cConfStateM = CONFena
28-
, i2cClaim = False
29-
, i2cWrite = False
30-
, i2cDin = repeat low
31-
, i2cLutIndex = 0
32-
, i2cFault = False
29+
confInit = ConfS { i2cConfStateM = CONFena
30+
, i2cConfClaim = False
31+
, i2cConfOp = Nothing
32+
, i2cConfLutIndex = 0
33+
, i2cConfFault = False
3334
}
3435

3536
configT
@@ -38,7 +39,7 @@ configT
3839
-> SimIO ConfO
3940
configT s0 (rst,ena,cmdAck,rxAck,al) = do
4041
s <- readReg s0
41-
let ConfS confStateM claim write din lutIndex fault = s
42+
let ConfS confStateM claim i2cOp lutIndex fault = s
4243

4344
let i2cSlvAddr = 0x34 :: BitVector 8
4445

@@ -51,88 +52,84 @@ configT s0 (rst,ena,cmdAck,rxAck,al) = do
5152
sNext <- if rst then pure confInit else case confStateM of
5253
CONFena
5354
| ena && not done
54-
-> pure s { i2cConfStateM = CONFaddr }
55+
-> pure s { i2cConfStateM = CONFaddr
56+
, i2cConfClaim = True
57+
}
5558
| done
5659
-> do display "done"
5760
pure s
5861

5962
CONFaddr
60-
-> pure s { i2cConfStateM = CONFaddrAck
61-
, i2cClaim = True
62-
, i2cWrite = True
63-
, i2cDin = unpack i2cSlvAddr
64-
}
63+
-> do
64+
display $ "CONFaddr, writing: " <> showHex i2cSlvAddr ""
65+
pure s { i2cConfStateM = CONFaddrAck
66+
, i2cConfOp = Just (WriteData (unpack i2cSlvAddr))
67+
}
6568

6669
CONFaddrAck
6770
| success
68-
-> do display "CONFaddrAck"
69-
pure s { i2cConfStateM = CONFreg
70-
, i2cWrite = False
71+
-> if rxAck then do
72+
display "CONFaddrAck"
73+
pure s { i2cConfStateM = CONFreg
74+
, i2cConfOp = Nothing
75+
}
76+
else do
77+
display "Failure CONFaddr"
78+
pure s { i2cConfStateM = CONFena
79+
, i2cConfFault = True
7180
}
7281

7382
CONFreg
74-
-> if not rxAck then do
83+
-> do
84+
display $
85+
"CONFreg, writing: " <> showHex (fst lutData) "" <>
86+
", lutIndex: " <> show lutIndex
87+
pure s { i2cConfStateM = CONFregAck
88+
, i2cConfOp = Just (WriteData (unpack (fst lutData)))
89+
}
90+
CONFregAck
91+
| success
92+
-> if rxAck then do
7593
display "Success CONFreg"
76-
pure s { i2cConfStateM = CONFregAck
77-
, i2cWrite = True
78-
, i2cDin = unpack (fst lutData)
79-
, i2cFault = False
94+
pure s { i2cConfStateM = CONFdata
95+
, i2cConfOp = Nothing
8096
}
8197
else do
8298
display "Failure CONFreg"
83-
_ <- finish 1
8499
pure s { i2cConfStateM = CONFena
85-
, i2cFault = True
100+
, i2cConfFault = True
86101
}
87102

88-
CONFregAck
89-
| success
90-
-> do display "CONFregAck"
91-
pure s { i2cConfStateM = CONFdata
92-
, i2cWrite = False
93-
}
94-
95103
CONFdata
96-
-> if not rxAck then do
104+
-> do display $ "CONFdata, writing: " <> showHex (snd lutData) ""
105+
pure s { i2cConfStateM = CONFdataAck
106+
, i2cConfOp = Just (WriteData (unpack (snd lutData)))
107+
}
108+
CONFdataAck
109+
| success
110+
-> if rxAck then do
97111
display "Success CONFdata"
98-
pure s { i2cConfStateM = CONFdataAck
99-
, i2cWrite = True
100-
, i2cClaim = False
101-
, i2cDin = unpack (snd lutData)
102-
, i2cFault = False
112+
pure s { i2cConfStateM = CONFstop
113+
, i2cConfOp = Nothing
103114
}
104115
else do
105116
display "Failure CONFdata"
106-
_ <- finish 1
107117
pure s { i2cConfStateM = CONFena
108-
, i2cFault = True
118+
, i2cConfFault = True
109119
}
110120

111-
CONFdataAck
112-
| success
113-
-> do display "CONFdataAck"
114-
pure s { i2cConfStateM = CONFstop
115-
, i2cWrite = False
116-
}
117-
118121
CONFstop
119-
-> if not rxAck then do
122+
-> do
120123
display "Success CONFstop"
121-
pure s { i2cConfStateM = CONFena
122-
, i2cLutIndex = lutIndex + 1
123-
, i2cFault = False
124-
}
125-
else do
126-
display "Failure CONFstop"
127-
_ <- finish 1
128-
pure s { i2cConfStateM = CONFena
129-
, i2cFault = True
124+
pure s { i2cConfStateM = CONFena
125+
, i2cConfClaim = False
126+
, i2cConfLutIndex = lutIndex + 1
130127
}
131128

132129
_ -> pure s
133130

134131
writeReg s0 sNext
135-
pure (claim,write,pack din,done,fault)
132+
pure (claim,i2cOp,done,fault)
136133

137134
configLut :: Index 16 -> (BitVector 8, BitVector 8)
138135
configLut i

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