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leonschoorlleonschoorl
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Remove now unused KnownDomain constraints
For some functions we add explicit foralls, so the order of the type arguments stays the same.
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12 files changed

+96
-139
lines changed

12 files changed

+96
-139
lines changed

‎clash-prelude/src/Clash/Class/AutoReg/Internal.hs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,7 @@ class NFDataX a => AutoReg a where
107107
-- This is the version with explicit clock\/reset\/enable inputs,
108108
-- "Clash.Prelude" exports an implicit version of this: 'Clash.Prelude.autoReg'
109109
autoReg
110-
:: (HasCallStack, KnownDomain dom)
110+
:: HasCallStack
111111
=> Clock dom -> Reset dom -> Enable dom
112112
-> a -- ^ Reset value
113113
-> Signal dom a
@@ -164,7 +164,7 @@ instance AutoReg a => AutoReg (Maybe a) where
164164

165165
instance (KnownNat n, AutoReg a) => AutoReg (Vec n a) where
166166
autoReg
167-
:: forall dom. (HasCallStack, KnownDomain dom)
167+
:: forall dom. HasCallStack
168168
=> Clock dom -> Reset dom -> Enable dom
169169
-> Vec n a -- ^ Reset value
170170
-> Signal dom (Vec n a)

‎clash-prelude/src/Clash/Explicit/BlockRam/Model.hs

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ import GHC.TypeNats (KnownNat)
2525
import Clash.Promoted.Nat (SNat(..), natToNum)
2626
import Clash.Signal.Bundle (Bundle(bundle))
2727
import Clash.Signal.Internal
28-
(KnownDomain(..), Clock (..), Signal (..), ClockAB (..), clockTicks)
28+
(Clock (..), Signal (..), ClockAB (..), clockTicks)
2929
import Clash.Sized.Index (Index)
3030
import Clash.XException (XException(..), NFDataX(..), seqX)
3131
import Clash.XException.MaybeX (MaybeX(..), toMaybeX, andX)
@@ -218,8 +218,6 @@ tdpbramModel ::
218218
forall nAddrs domA domB a writeEnable .
219219
( HasCallStack
220220
, KnownNat nAddrs
221-
, KnownDomain domA
222-
, KnownDomain domB
223221
, NFDataX a
224222
) =>
225223
TdpbramModelConfig writeEnable a ->

‎clash-prelude/src/Clash/Explicit/Mealy.hs

Lines changed: 13 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ module Clash.Explicit.Mealy
2727
where
2828

2929
import Clash.Explicit.Signal
30-
(KnownDomain, Bundle (..), Clock, Reset, Signal, Enable, register)
30+
(Bundle (..), Clock, Reset, Signal, Enable, register)
3131
import Clash.XException (NFDataX)
3232

3333
import Control.Monad.State.Strict
@@ -100,8 +100,7 @@ delayTop clk rst en = mealyS clk rst en delayS initialDelayState
100100
-- s' = x * y + s
101101
--
102102
-- mac
103-
-- :: 'KnownDomain' dom
104-
-- => 'Clock' dom
103+
-- :: 'Clock' dom
105104
-- -> 'Reset' dom
106105
-- -> 'Enable' dom
107106
-- -> 'Signal' dom (Int, Int)
@@ -118,8 +117,7 @@ delayTop clk rst en = mealyS clk rst en delayS initialDelayState
118117
--
119118
-- @
120119
-- dualMac
121-
-- :: 'KnownDomain' dom
122-
-- => 'Clock' dom
120+
-- :: 'Clock' dom
123121
-- -> 'Reset' dom
124122
-- -> 'Enable' dom
125123
-- -> ('Signal' dom Int, 'Signal' dom Int)
@@ -131,8 +129,8 @@ delayTop clk rst en = mealyS clk rst en delayS initialDelayState
131129
-- s2 = 'mealy' clk rst en macT 0 ('bundle' (b,y))
132130
-- @
133131
mealy
134-
:: ( KnownDomain dom
135-
, NFDataX s )
132+
:: forall dom s i o
133+
. NFDataX s
136134
=> Clock dom
137135
-- ^ 'Clock' to synchronize to
138136
-> Reset dom
@@ -177,8 +175,8 @@ mealy clk rst en f iS =
177175
-- out <- uses history last
178176
-- return (Just out)
179177
--
180-
-- delayTop ::'KnownDomain' dom
181-
-- => 'Clock' dom
178+
-- delayTop ::
179+
-- 'Clock' dom
182180
-- -> 'Reset' dom
183181
-- -> 'Enable' dom
184182
-- -> ('Signal' dom Int -> 'Signal' dom (Maybe Int))
@@ -189,8 +187,8 @@ mealy clk rst en f iS =
189187
-- [Nothing,Nothing,Nothing,Nothing,Just 1,Just 2,Just 3]
190188
--
191189
mealyS
192-
:: ( KnownDomain dom
193-
, NFDataX s )
190+
:: forall dom s i o
191+
. NFDataX s
194192
=> Clock dom
195193
-- ^ 'Clock' to synchronize to
196194
-> Reset dom
@@ -236,8 +234,8 @@ mealyS clk rst en f iS =
236234
-- (i2,b2) = 'mealyB' clk rst en f 3 (c,i1)
237235
-- @
238236
mealyB
239-
:: ( KnownDomain dom
240-
, NFDataX s
237+
:: forall dom s i o
238+
. ( NFDataX s
241239
, Bundle i
242240
, Bundle o )
243241
=> Clock dom
@@ -256,8 +254,8 @@ mealyB clk rst en f iS i = unbundle (mealy clk rst en f iS (bundle i))
256254

257255
-- | A version of 'mealyS' that does automatic 'Bundle'ing, see 'mealyB' for details.
258256
mealySB
259-
:: ( KnownDomain dom
260-
, NFDataX s
257+
:: forall dom s i o
258+
. ( NFDataX s
261259
, Bundle i
262260
, Bundle o )
263261
=> Clock dom

‎clash-prelude/src/Clash/Explicit/Moore.hs

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ module Clash.Explicit.Moore
2626
where
2727

2828
import Clash.Explicit.Signal
29-
(KnownDomain, Bundle (..), Clock, Reset, Signal, Enable, register)
29+
(Bundle (..), Clock, Reset, Signal, Enable, register)
3030
import Clash.XException (NFDataX)
3131

3232
{- $setup
@@ -47,8 +47,7 @@ import Clash.XException (NFDataX)
4747
-- macT s (x,y) = x * y + s
4848
--
4949
-- mac
50-
-- :: 'KnownDomain' dom
51-
-- => 'Clock' dom
50+
-- :: 'Clock' dom
5251
-- -> 'Reset' dom
5352
-- -> 'Enable' dom
5453
-- -> 'Signal' dom (Int, Int)
@@ -65,8 +64,7 @@ import Clash.XException (NFDataX)
6564
--
6665
-- @
6766
-- dualMac
68-
-- :: 'KnownDomain' dom
69-
-- => 'Clock' dom
67+
-- :: 'Clock' dom
7068
-- -> 'Reset' dom
7169
-- -> 'Enable' dom
7270
-- -> ('Signal' dom Int, 'Signal' dom Int)
@@ -78,8 +76,8 @@ import Clash.XException (NFDataX)
7876
-- s2 = 'moore' clk rst en macT id 0 ('bundle' (b,y))
7977
-- @
8078
moore
81-
:: ( KnownDomain dom
82-
, NFDataX s )
79+
:: forall dom s i o
80+
. NFDataX s
8381
=> Clock dom
8482
-- ^ 'Clock' to synchronize to
8583
-> Reset dom
@@ -102,8 +100,8 @@ moore clk rst en ft fo iS =
102100
-- | Create a synchronous function from a combinational function describing
103101
-- a moore machine without any output logic
104102
medvedev
105-
:: ( KnownDomain dom
106-
, NFDataX s )
103+
:: forall dom s i
104+
. NFDataX s
107105
=> Clock dom
108106
-> Reset dom
109107
-> Enable dom
@@ -141,8 +139,8 @@ medvedev clk rst en tr st = moore clk rst en tr id st
141139
-- (i2,b2) = 'mooreB' clk rst en t o 3 (c,i1)
142140
-- @
143141
mooreB
144-
:: ( KnownDomain dom
145-
, NFDataX s
142+
:: forall dom s i o
143+
. ( NFDataX s
146144
, Bundle i
147145
, Bundle o )
148146
=> Clock dom
@@ -164,8 +162,8 @@ mooreB clk rst en ft fo iS i = unbundle (moore clk rst en ft fo iS (bundle i))
164162

165163
-- | A version of 'medvedev' that does automatic 'Bundle'ing
166164
medvedevB
167-
:: ( KnownDomain dom
168-
, NFDataX s
165+
:: forall dom s i
166+
. ( NFDataX s
169167
, Bundle i
170168
, Bundle s )
171169
=> Clock dom

‎clash-prelude/src/Clash/Explicit/Prelude.hs

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -229,8 +229,8 @@ functions a type class called 'Clash.Class.Parity.Parity' is available at
229229
-- [1 :> 0 :> 0 :> 0 :> Nil,2 :> 1 :> 0 :> 0 :> Nil,3 :> 2 :> 1 :> 0 :> Nil,4 :> 3 :> 2 :> 1 :> Nil,5 :> 4 :> 3 :> 2 :> Nil,...
230230
-- ...
231231
window
232-
:: ( KnownNat n
233-
, KnownDomain dom
232+
:: forall n dom a
233+
. ( KnownNat n
234234
, NFDataX a
235235
, Default a
236236
)
@@ -255,8 +255,7 @@ window clk rst en x = res
255255
--
256256
-- @
257257
-- windowD3
258-
-- :: KnownDomain dom
259-
-- -> Clock dom
258+
-- :: Clock dom
260259
-- -> Enable dom
261260
-- -> Reset dom
262261
-- -> 'Signal' dom Int
@@ -271,7 +270,7 @@ windowD
271270
:: ( KnownNat n
272271
, NFDataX a
273272
, Default a
274-
, KnownDomain dom )
273+
)
275274
=> Clock dom
276275
-- ^ Clock to which the incoming signal is synchronized
277276
-> Reset dom

‎clash-prelude/src/Clash/Explicit/Prelude/Safe.hs

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -186,8 +186,8 @@ functions a type class called 'Clash.Class.Parity.Parity' is available at
186186
-- [(8,8),(8,8),(1,1),(2,2),(3,3)...
187187
-- ...
188188
registerB
189-
:: ( KnownDomain dom
190-
, NFDataX a
189+
:: forall dom a
190+
. ( NFDataX a
191191
, Bundle a )
192192
=> Clock dom
193193
-> Reset dom
@@ -201,8 +201,8 @@ registerB clk rst en i =
201201

202202
-- | Give a pulse when the 'Signal' goes from 'minBound' to 'maxBound'
203203
isRising
204-
:: ( KnownDomain dom
205-
, NFDataX a
204+
:: forall dom a
205+
. ( NFDataX a
206206
, Bounded a
207207
, Eq a )
208208
=> Clock dom
@@ -219,8 +219,8 @@ isRising clk rst en is s = liftA2 edgeDetect prev s
219219

220220
-- | Give a pulse when the 'Signal' goes from 'maxBound' to 'minBound'
221221
isFalling
222-
:: ( KnownDomain dom
223-
, NFDataX a
222+
:: forall dom a
223+
. ( NFDataX a
224224
, Bounded a
225225
, Eq a )
226226
=> Clock dom
@@ -240,8 +240,7 @@ isFalling clk rst en is s = liftA2 edgeDetect prev s
240240
-- @'Clash.Explicit.Signal.mux'@, in order to delay a register by a known amount.
241241
riseEvery
242242
:: forall dom n
243-
. KnownDomain dom
244-
=> Clock dom
243+
. Clock dom
245244
-> Reset dom
246245
-> Enable dom
247246
-> SNat n
@@ -258,8 +257,7 @@ riseEvery clk rst en SNat = moore clk rst en transfer output 0 (pure ())
258257
-- | Oscillate a @'Bool'@ for a given number of cycles, given the starting state.
259258
oscillate
260259
:: forall dom n
261-
. KnownDomain dom
262-
=> Clock dom
260+
. Clock dom
263261
-> Reset dom
264262
-> Enable dom
265263
-> Bool

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