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leonschoorlleonschoorl
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Remove dummy constraint ZKnownDomain
1 parent f08bdc0 commit c896f21

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10 files changed

+107
-162
lines changed

10 files changed

+107
-162
lines changed

‎clash-prelude/src/Clash/Explicit/BlockRam.hs

Lines changed: 22 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -443,7 +443,7 @@ import Clash.Annotations.Primitive
443443
(Primitive(InlineYamlPrimitive), HDL(..), hasBlackBox)
444444
import Clash.Class.Num (SaturationMode(SatBound), satSucc)
445445
import Clash.Explicit.BlockRam.Model (TdpbramModelConfig(..), tdpbramModel)
446-
import Clash.Explicit.Signal (ZKnownDomain, Enable, register, fromEnable)
446+
import Clash.Explicit.Signal (Enable, register, fromEnable)
447447
import Clash.Promoted.Nat (SNat(..))
448448
import Clash.Signal.Bundle (unbundle)
449449
import Clash.Signal.Internal
@@ -905,8 +905,7 @@ blockRamU clk rst0 en rstStrategy n@SNat initF rd0 mw0 =
905905
-- | blockRAMU primitive
906906
blockRamU#
907907
:: forall n dom a
908-
. ( ZKnownDomain dom
909-
, HasCallStack
908+
. ( HasCallStack
910909
, NFDataX a )
911910
=> Clock dom
912911
-- ^ 'Clock' to synchronize to
@@ -938,16 +937,15 @@ blockRamU# clk en SNat =
938937
{-# ANN blockRamU# (
939938
let
940939
bbName = show 'blockRamU#
941-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
940+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
942941
in
943942
InlineYamlPrimitive [SystemVerilog] [__i|
944943
BlackBox:
945944
name: '#{bbName}'
946945
kind: Declaration
947946
type: |-
948947
blockRamU\#
949-
:: ( ZKnownDomain dom ARG[0]
950-
, HasCallStack -- ARG[1]
948+
:: ( HasCallStack -- ARG[1]
951949
, Undefined a ) -- ARG[2]
952950
=> Clock dom -- clk, ARG[3]
953951
-> Enable dom -- en, ARG[4]
@@ -987,7 +985,7 @@ blockRamU# clk en SNat =
987985
{-# ANN blockRamU# (
988986
let
989987
bbName = show 'blockRamU#
990-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
988+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
991989
in
992990
InlineYamlPrimitive [Verilog] [__i|
993991
BlackBox:
@@ -996,8 +994,7 @@ blockRamU# clk en SNat =
996994
outputUsage: NonBlocking
997995
type: |-
998996
blockRamU\#
999-
:: ( ZKnownDomain dom ARG[0]
1000-
, HasCallStack -- ARG[1]
997+
:: ( HasCallStack -- ARG[1]
1001998
, Undefined a ) -- ARG[2]
1002999
=> Clock dom -- clk, ARG[3]
10031000
-> Enable dom -- en, ARG[4]
@@ -1037,7 +1034,7 @@ blockRamU# clk en SNat =
10371034
{-# ANN blockRamU# (
10381035
let
10391036
bbName = show 'blockRamU#
1040-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
1037+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
10411038
in
10421039
InlineYamlPrimitive [VHDL] [__i|
10431040
BlackBox:
@@ -1046,8 +1043,7 @@ blockRamU# clk en SNat =
10461043
outputUsage: NonBlocking
10471044
type: |-
10481045
blockRamU\#
1049-
:: ( ZKnownDomain dom ARG[0]
1050-
, HasCallStack -- ARG[1]
1046+
:: ( HasCallStack -- ARG[1]
10511047
, Undefined a ) -- ARG[2]
10521048
=> Clock dom -- clk, ARG[3]
10531049
-> Enable dom -- en, ARG[4]
@@ -1161,8 +1157,7 @@ blockRam1 clk rst0 en rstStrategy n@SNat a rd0 mw0 =
11611157
-- | blockRAM1 primitive
11621158
blockRam1#
11631159
:: forall n dom a
1164-
. ( ZKnownDomain dom
1165-
, HasCallStack
1160+
. ( HasCallStack
11661161
, NFDataX a )
11671162
=> Clock dom
11681163
-- ^ 'Clock' to synchronize to
@@ -1191,16 +1186,15 @@ blockRam1# clk en n a =
11911186
{-# ANN blockRam1# (
11921187
let
11931188
bbName = show 'blockRam1#
1194-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
1189+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
11951190
in
11961191
InlineYamlPrimitive [SystemVerilog] [__i|
11971192
BlackBox:
11981193
name: '#{bbName}'
11991194
kind: Declaration
12001195
type: |-
12011196
blockRam1\#
1202-
:: ( ZKnownDomain dom ARG[0]
1203-
, HasCallStack -- ARG[1]
1197+
:: ( HasCallStack -- ARG[1]
12041198
, Undefined a ) -- ARG[2]
12051199
=> Clock dom -- clk, ARG[3]
12061200
-> Enable dom -- en, ARG[4]
@@ -1244,7 +1238,7 @@ blockRam1# clk en n a =
12441238
{-# ANN blockRam1# (
12451239
let
12461240
bbName = show 'blockRam1#
1247-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
1241+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
12481242
in
12491243
InlineYamlPrimitive [Verilog] [__i|
12501244
BlackBox:
@@ -1253,8 +1247,7 @@ blockRam1# clk en n a =
12531247
outputUsage: NonBlocking
12541248
type: |-
12551249
blockRam1\#
1256-
:: ( ZKnownDomain dom ARG[0]
1257-
, HasCallStack -- ARG[1]
1250+
:: ( HasCallStack -- ARG[1]
12581251
, Undefined a ) -- ARG[2]
12591252
=> Clock dom -- clk, ARG[3]
12601253
-> Enable dom -- en, ARG[4]
@@ -1301,7 +1294,7 @@ blockRam1# clk en n a =
13011294
{-# ANN blockRam1# (
13021295
let
13031296
bbName = show 'blockRam1#
1304-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
1297+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
13051298
in
13061299
InlineYamlPrimitive [VHDL] [__i|
13071300
BlackBox:
@@ -1310,8 +1303,7 @@ blockRam1# clk en n a =
13101303
outputUsage: NonBlocking
13111304
type: |-
13121305
blockRam1\#
1313-
:: ( ZKnownDomain dom ARG[0]
1314-
, HasCallStack -- ARG[1]
1306+
:: ( HasCallStack -- ARG[1]
13151307
, Undefined a ) -- ARG[2]
13161308
=> Clock dom -- clk, ARG[3]
13171309
-> Enable dom -- en, ARG[4]
@@ -1368,8 +1360,7 @@ blockRam1# clk en n a =
13681360
-- | blockRAM primitive
13691361
blockRam#
13701362
:: forall dom a n
1371-
. ( ZKnownDomain dom
1372-
, HasCallStack
1363+
. ( HasCallStack
13731364
, NFDataX a )
13741365
=> Clock dom
13751366
-- ^ 'Clock' to synchronize to
@@ -1464,16 +1455,15 @@ blockRam# _ _ _ = error "blockRam#: dynamic clocks not supported"
14641455
{-# ANN blockRam# (
14651456
let
14661457
bbName = show 'blockRam#
1467-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
1458+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
14681459
in
14691460
InlineYamlPrimitive [SystemVerilog] [__i|
14701461
BlackBox:
14711462
name: '#{bbName}'
14721463
kind: Declaration
14731464
type: |-
14741465
blockRam\#
1475-
:: ( ZKnownDomain dom ARG[0]
1476-
, HasCallStack -- ARG[1]
1466+
:: ( HasCallStack -- ARG[1]
14771467
, Undefined a ) -- ARG[2]
14781468
=> Clock dom -- clk, ARG[3]
14791469
-> Enable dom -- en, ARG[4]
@@ -1516,7 +1506,7 @@ blockRam# _ _ _ = error "blockRam#: dynamic clocks not supported"
15161506
{-# ANN blockRam# (
15171507
let
15181508
bbName = show 'blockRam#
1519-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
1509+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
15201510
in
15211511
InlineYamlPrimitive [Verilog] [__i|
15221512
BlackBox:
@@ -1525,8 +1515,7 @@ blockRam# _ _ _ = error "blockRam#: dynamic clocks not supported"
15251515
outputUsage: NonBlocking
15261516
type: |-
15271517
blockRam\#
1528-
:: ( ZKnownDomain dom ARG[0]
1529-
, HasCallStack -- ARG[1]
1518+
:: ( HasCallStack -- ARG[1]
15301519
, Undefined a ) -- ARG[2]
15311520
=> Clock dom -- clk, ARG[3]
15321521
=> Enable dom -- en, ARG[4]
@@ -1574,7 +1563,7 @@ blockRam# _ _ _ = error "blockRam#: dynamic clocks not supported"
15741563
{-# ANN blockRam# (
15751564
let
15761565
bbName = show 'blockRam#
1577-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
1566+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< _ = ((0 :: Int)...)
15781567
in
15791568
InlineYamlPrimitive [VHDL] [__i|
15801569
BlackBox:
@@ -1583,8 +1572,7 @@ blockRam# _ _ _ = error "blockRam#: dynamic clocks not supported"
15831572
outputUsage: NonBlocking
15841573
type: |-
15851574
blockRam\#
1586-
:: ( ZKnownDomain dom ARG[0]
1587-
, HasCallStack -- ARG[1]
1575+
:: ( HasCallStack -- ARG[1]
15881576
, Undefined a ) -- ARG[2]
15891577
=> Clock dom -- clk, ARG[3]
15901578
-> Enable dom -- en, ARG[4]

‎clash-prelude/src/Clash/Explicit/BlockRam/Blob.hs

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ import Clash.Annotations.Primitive (hasBlackBox)
5757
import Clash.Class.BitPack.Internal (BitPack, BitSize)
5858
import Clash.Explicit.BlockRam.Internal
5959
(MemBlob(..), packBVs, unpackMemBlob, unpackMemBlob0)
60-
import Clash.Explicit.Signal (ZKnownDomain, Enable, fromEnable)
60+
import Clash.Explicit.Signal (Enable, fromEnable)
6161
import Clash.Promoted.Nat (natToInteger, natToNum)
6262
import Clash.Signal.Bundle (unbundle)
6363
import Clash.Signal.Internal (Clock, Signal(..), (.&&.))
@@ -153,8 +153,7 @@ blockRamBlobPow2 = blockRamBlob
153153
-- | blockRAMBlob primitive
154154
blockRamBlob#
155155
:: forall dom m n
156-
. ZKnownDomain dom
157-
=> Clock dom
156+
. Clock dom
158157
-- ^ 'Clock' to synchronize to
159158
-> Enable dom
160159
-- ^ 'Enable' line
@@ -241,16 +240,15 @@ blockRamBlob# !_ gen content@MemBlob{} = \rd wen waS wd -> runST $ do
241240
{-# ANN blockRamBlob# (
242241
let
243242
bbName = show 'blockRamBlob#
244-
_arg0 :< arg1 :< arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< _ = ((0 :: Int)...)
243+
arg1 :< arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< _ = ((0 :: Int)...)
245244
in
246245
InlineYamlPrimitive [SystemVerilog] [__i|
247246
BlackBox:
248247
name: '#{bbName}'
249248
kind: Declaration
250249
type: |-
251250
blockRamBlob\#
252-
:: ZKnownDomain dom -- ARG[0]
253-
=> Clock dom -- clk, ARG[1]
251+
:: Clock dom -- clk, ARG[1]
254252
-> Enable dom -- en, ARG[2]
255253
-> MemBlob n m -- init, ARG[3]
256254
-> Signal dom Int -- rd, ARG[4]
@@ -291,7 +289,7 @@ blockRamBlob# !_ gen content@MemBlob{} = \rd wen waS wd -> runST $ do
291289
{-# ANN blockRamBlob# (
292290
let
293291
bbName = show 'blockRamBlob#
294-
_arg0 :< arg1 :< arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< _ = ((0 :: Int)...)
292+
arg1 :< arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< _ = ((0 :: Int)...)
295293
in
296294
InlineYamlPrimitive [Verilog] [__i|
297295
BlackBox:
@@ -300,8 +298,7 @@ blockRamBlob# !_ gen content@MemBlob{} = \rd wen waS wd -> runST $ do
300298
outputUsage: NonBlocking
301299
type: |-
302300
blockRamBlob\#
303-
:: ZKnownDomain dom -- ARG[0]
304-
=> Clock dom -- clk, ARG[1]
301+
:: Clock dom -- clk, ARG[1]
305302
-> Enable dom -- en, ARG[2]
306303
-> MemBlob n m -- init, ARG[3]
307304
-> Signal dom Int -- rd, ARG[4]
@@ -347,7 +344,7 @@ blockRamBlob# !_ gen content@MemBlob{} = \rd wen waS wd -> runST $ do
347344
{-# ANN blockRamBlob# (
348345
let
349346
bbName = show 'blockRamBlob#
350-
_arg0 :< arg1 :< arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< _ = ((0 :: Int)...)
347+
arg1 :< arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< _ = ((0 :: Int)...)
351348
in
352349
InlineYamlPrimitive [VHDL] [__i|
353350
BlackBox:
@@ -356,8 +353,7 @@ blockRamBlob# !_ gen content@MemBlob{} = \rd wen waS wd -> runST $ do
356353
outputUsage: NonBlocking
357354
type: |-
358355
blockRamBlob\#
359-
:: ZKnownDomain dom -- ARG[0]
360-
=> Clock dom -- clk, ARG[1]
356+
:: Clock dom -- clk, ARG[1]
361357
-> Enable dom -- en, ARG[2]
362358
-> MemBlob n m -- init, ARG[3]
363359
-> Signal dom Int -- rd, ARG[4]

‎clash-prelude/src/Clash/Explicit/BlockRam/File.hs

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ import Clash.Class.BitPack (BitPack, BitSize, pack)
124124
import Clash.Promoted.Nat (SNat (..), pow2SNat, natToNum, snatToNum)
125125
import Clash.Sized.Internal.BitVector (Bit(..), BitVector(..), undefined#)
126126
import Clash.Signal.Internal
127-
(Clock(..), Signal (..), Enable, ZKnownDomain, fromEnable, (.&&.))
127+
(Clock(..), Signal (..), Enable, fromEnable, (.&&.))
128128
import Clash.Signal.Bundle (unbundle)
129129
import Clash.Sized.Unsigned (Unsigned)
130130
import Clash.XException (maybeIsX, seqX, fromJustX, NFDataX(..), XException (..))
@@ -322,7 +322,7 @@ memFile care = foldr (\e -> showsBV $ pack e) ""
322322
-- | blockRamFile primitive
323323
blockRamFile#
324324
:: forall m dom n
325-
. (ZKnownDomain dom, KnownNat m, HasCallStack)
325+
. (KnownNat m, HasCallStack)
326326
=> Clock dom
327327
-- ^ 'Clock' to synchronize to
328328
-> Enable dom
@@ -437,16 +437,15 @@ blockRamFile# _ _ _ _ = error "blockRamFile#: dynamic clocks not supported"
437437
{-# ANN blockRamFile# (
438438
let
439439
bbName = show 'blockRamFile#
440-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
440+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
441441
in
442442
InlineYamlPrimitive [SystemVerilog] [__i|
443443
BlackBox:
444444
name: '#{bbName}'
445445
kind: Declaration
446446
type: |-
447447
blockRamFile\#
448-
:: ( ZKnownDomain dom -- ARG[0]
449-
, KnownNat m -- ARG[1]
448+
:: ( KnownNat m -- ARG[1]
450449
, HasCallStack ) -- ARG[2]
451450
=> Clock dom -- clk, ARG[3]
452451
=> Enable dom -- en, ARG[4]
@@ -493,7 +492,7 @@ blockRamFile# _ _ _ _ = error "blockRamFile#: dynamic clocks not supported"
493492
{-# ANN blockRamFile# (
494493
let
495494
bbName = show 'blockRamFile#
496-
_arg0 :< _arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
495+
_arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
497496
in
498497
InlineYamlPrimitive [Verilog] [__i|
499498
BlackBox:
@@ -502,8 +501,7 @@ blockRamFile# _ _ _ _ = error "blockRamFile#: dynamic clocks not supported"
502501
outputUsage: NonBlocking
503502
type: |-
504503
blockRamFile\#
505-
:: ( ZKnownDomain dom -- ARG[0]
506-
, KnownNat m -- ARG[1]
504+
:: ( KnownNat m -- ARG[1]
507505
, HasCallStack ) -- ARG[2]
508506
=> Clock dom -- clk, ARG[3]
509507
=> Enable dom -- en, ARG[4]
@@ -547,7 +545,7 @@ blockRamFile# _ _ _ _ = error "blockRamFile#: dynamic clocks not supported"
547545
{-# ANN blockRamFile# (
548546
let
549547
bbName = show 'blockRamFile#
550-
_arg0 :< arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
548+
arg1 :< _arg2 :< arg3 :< arg4 :< arg5 :< arg6 :< arg7 :< arg8 :< arg9 :< arg10 :< _ = ((0 :: Int)...)
551549
in
552550
InlineYamlPrimitive [VHDL] [__i|
553551
BlackBox:
@@ -556,8 +554,7 @@ blockRamFile# _ _ _ _ = error "blockRamFile#: dynamic clocks not supported"
556554
outputUsage: NonBlocking
557555
type: |-
558556
blockRamFile\#
559-
:: ( ZKnownDomain dom -- ARG[0]
560-
, KnownNat m -- ARG[1]
557+
:: ( KnownNat m -- ARG[1]
561558
, HasCallStack ) -- ARG[2]
562559
=> Clock dom -- clk, ARG[3]
563560
=> Enable dom -- en, ARG[4]

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