Verilog blackbox for `iterateI` uses `wire` for sequential assignments

[lmbollen]

The blackbox for verilog uses wire instead of reg which causes Vivado to throw the following tantrum:

ERROR: [Synth 8-2577] procedural assignment to a non-register iterateI_ho1_0_res_21 is not permitted, left-hand side should be reg/integer/time/genvar

on the folllowing piece of verilog code:

  wire [63:0] iterateI_ho1_0_res_21;
  wire [63:0] iterateI_ho1_1_res_1;
  wire [63:0] iterateI_ho1_2_res_1;
  // delay begin
  always @(posedge bFwd_66[1240:1240]) begin : c$app_arg_361_delay_2
    iterateI_ho1_0_res_21 <= cnt;
  end
  // delay end

  // delay begin
  always @(posedge bFwd_66[1240:1240]) begin : c$app_arg_361_delay_0_0
    iterateI_ho1_1_res_1 <= iterateI_ho1_0_res_21;
  end
  // delay end

  // delay begin
  always @(posedge bFwd_66[1240:1240]) begin : c$app_arg_361_delay_1_1
    iterateI_ho1_2_res_1 <= iterateI_ho1_1_res_1;
  end
  // delay end

Reproducer:

module Example where

import Clash.Prelude

delayedCounter ::
  forall dom d n.
  (HiddenClockResetEnable dom, KnownNat d, KnownNat n) =>
  SNat d ->
  Signal dom (Unsigned n)
delayedCounter d = last $ iterate (succSNat d) dflipflop cnt
 where
  cnt = register 0 (cnt + 1)

topEntity :: Clock System -> Reset System -> Enable System -> Signal System (Unsigned 8)
topEntity = exposeClockResetEnable $ delayedCounter d3

I tried to quickly reproduce failure with yosys but "unfortunately" yosys did not care and just synthesized.