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bjorn-helgaasbjorn-helgaas
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Merge branch 'remotes/lorenzo/pci/mvebu'
- Implement pci_remap_iospace() for ARM so mvebu can use devm_pci_remap_iospace() instead of the previous ARM-specific pci_ioremap_io() interface (Pali Rohár) - Use the standard pci_host_probe() instead of the device-specific mvebu_pci_host_probe() (Pali Rohár) - Replace all uses of ARM-specific pci_ioremap_io() with the ARM implementation of the standard pci_remap_iospace() interface and remove pci_ioremap_io() (Pali Rohár) - Skip initializing invalid Root Ports (Pali Rohár) - Check for errors from pci_bridge_emul_init() (Pali Rohár) - Ignore any bridges at non-zero function numbers (Pali Rohár) - Return ~0 data for invalid config read size (Pali Rohár) - Disallow mapping interrupts on emulated bridges (Pali Rohár) - Clear Root Port Memory & I/O Space Enable and Bus Master Enable at initialization (Pali Rohár) - Make type bits in Root Port I/O Base register read-only (Pali Rohár) - Disable Root Port windows when base/limit set to invalid values (Pali Rohár) - Set controller to Root Complex mode (Pali Rohár) - Set Root Port Class Code to PCI Bridge (Pali Rohár) - Update emulated Root Port secondary bus numbers to better reflect the actual topology (Pali Rohár) - Add PCI_BRIDGE_CTL_BUS_RESET support to emulated Root Ports so pci_reset_secondary_bus() can reset connected devices (Pali Rohár) - Add PCI_EXP_DEVCTL Error Reporting Enable support to emulated Root Ports (Pali Rohár) - Add PCI_EXP_RTSTA PME Status bit support to emulated Root Ports (Pali Rohár) - Add DEVCAP2, DEVCTL2 and LNKCTL2 support to emulated Root Ports on Armada XP and newer devices (Pali Rohár) - Export mvebu-mbus.c symbols to allow pci-mvebu.c to be a module (Pali Rohár) - Add support for compiling as a module (Pali Rohár) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Add support for compiling driver as module bus: mvebu-mbus: Export symbols for public API window functions PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on emulated bridge PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridge PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridge PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge PCI: mvebu: Setup PCIe controller to Root Complex mode PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers PCI: mvebu: Do not modify PCI IO type bits in conf_write PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge PCI: mvebu: Disallow mapping interrupts on emulated bridges PCI: mvebu: Handle invalid size of read config request PCI: mvebu: Check that PCI bridge specified in DT has function number zero PCI: mvebu: Check for errors from pci_bridge_emul_init() call PCI: mvebu: Check for valid ports arm: ioremap: Remove unused ARM-specific function pci_ioremap_io() arm: ioremap: Replace pci_ioremap_io() usage by pci_remap_iospace() PCI: mvebu: Remove custom mvebu_pci_host_probe() function PCI: mvebu: Replace pci_ioremap_io() usage by devm_pci_remap_iospace() arm: ioremap: Implement standard PCI function pci_remap_iospace()
2 parents fc10f9d + 0746ae1 commit 0de15db

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10 files changed

+440
-149
lines changed

10 files changed

+440
-149
lines changed

‎arch/arm/include/asm/io.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,10 @@ void pci_ioremap_set_mem_type(int mem_type);
180180
static inline void pci_ioremap_set_mem_type(int mem_type) {}
181181
#endif
182182

183-
extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
183+
struct resource;
184+
185+
#define pci_remap_iospace pci_remap_iospace
186+
int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
184187

185188
/*
186189
* PCI configuration space mapping function.

‎arch/arm/mach-dove/pcie.c‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ static int num_pcie_ports;
3838
static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
3939
{
4040
struct pcie_port *pp;
41+
struct resource realio;
4142

4243
if (nr >= num_pcie_ports)
4344
return 0;
@@ -53,10 +54,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
5354

5455
orion_pcie_setup(pp->base);
5556

56-
if (pp->index == 0)
57-
pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
58-
else
59-
pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
57+
realio.start = sys->busnr * SZ_64K;
58+
realio.end = realio.start + SZ_64K - 1;
59+
pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
60+
DOVE_PCIE1_IO_PHYS_BASE);
6061

6162
/*
6263
* IORESOURCE_MEM

‎arch/arm/mach-iop32x/pci.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -185,6 +185,7 @@ iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
185185
int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
186186
{
187187
struct resource *res;
188+
struct resource realio;
188189

189190
if (nr != 0)
190191
return 0;
@@ -206,7 +207,9 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
206207

207208
pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
208209

209-
pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
210+
realio.start = 0;
211+
realio.end = realio.start + SZ_64K - 1;
212+
pci_remap_iospace(&realio, IOP3XX_PCI_LOWER_IO_PA);
210213

211214
return 1;
212215
}

‎arch/arm/mach-mv78xx0/pcie.c‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,7 @@ static void __init mv78xx0_pcie_preinit(void)
101101
static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
102102
{
103103
struct pcie_port *pp;
104+
struct resource realio;
104105

105106
if (nr >= num_pcie_ports)
106107
return 0;
@@ -115,7 +116,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
115116
orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
116117
orion_pcie_setup(pp->base);
117118

118-
pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
119+
realio.start = nr * SZ_64K;
120+
realio.end = realio.start + SZ_64K - 1;
121+
pci_remap_iospace(&realio, MV78XX0_PCIE_IO_PHYS_BASE(nr));
119122

120123
pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
121124

‎arch/arm/mach-orion5x/pci.c‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,7 @@ static struct pci_ops pcie_ops = {
142142
static int __init pcie_setup(struct pci_sys_data *sys)
143143
{
144144
struct resource *res;
145+
struct resource realio;
145146
int dev;
146147

147148
/*
@@ -164,7 +165,9 @@ static int __init pcie_setup(struct pci_sys_data *sys)
164165
pcie_ops.read = pcie_rd_conf_wa;
165166
}
166167

167-
pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
168+
realio.start = sys->busnr * SZ_64K;
169+
realio.end = realio.start + SZ_64K - 1;
170+
pci_remap_iospace(&realio, ORION5X_PCIE_IO_PHYS_BASE);
168171

169172
/*
170173
* Request resources.
@@ -466,6 +469,7 @@ static void __init orion5x_setup_pci_wins(void)
466469
static int __init pci_setup(struct pci_sys_data *sys)
467470
{
468471
struct resource *res;
472+
struct resource realio;
469473

470474
/*
471475
* Point PCI unit MBUS decode windows to DRAM space.
@@ -482,7 +486,9 @@ static int __init pci_setup(struct pci_sys_data *sys)
482486
*/
483487
orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
484488

485-
pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
489+
realio.start = sys->busnr * SZ_64K;
490+
realio.end = realio.start + SZ_64K - 1;
491+
pci_remap_iospace(&realio, ORION5X_PCI_IO_PHYS_BASE);
486492

487493
/*
488494
* Request resources

‎arch/arm/mm/ioremap.c‎

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -459,16 +459,20 @@ void pci_ioremap_set_mem_type(int mem_type)
459459
pci_ioremap_mem_type = mem_type;
460460
}
461461

462-
int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
462+
int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
463463
{
464-
BUG_ON(offset + SZ_64K - 1 > IO_SPACE_LIMIT);
464+
unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
465465

466-
return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
467-
PCI_IO_VIRT_BASE + offset + SZ_64K,
468-
phys_addr,
466+
if (!(res->flags & IORESOURCE_IO))
467+
return -EINVAL;
468+
469+
if (res->end > IO_SPACE_LIMIT)
470+
return -EINVAL;
471+
472+
return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
469473
__pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte));
470474
}
471-
EXPORT_SYMBOL_GPL(pci_ioremap_io);
475+
EXPORT_SYMBOL(pci_remap_iospace);
472476

473477
void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)
474478
{

‎drivers/bus/mvebu-mbus.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -914,13 +914,15 @@ int mvebu_mbus_add_window_remap_by_id(unsigned int target,
914914

915915
return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
916916
}
917+
EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_remap_by_id);
917918

918919
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
919920
phys_addr_t base, size_t size)
920921
{
921922
return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
922923
size, MVEBU_MBUS_NO_REMAP);
923924
}
925+
EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_by_id);
924926

925927
int mvebu_mbus_del_window(phys_addr_t base, size_t size)
926928
{
@@ -933,20 +935,23 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size)
933935
mvebu_mbus_disable_window(&mbus_state, win);
934936
return 0;
935937
}
938+
EXPORT_SYMBOL_GPL(mvebu_mbus_del_window);
936939

937940
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
938941
{
939942
if (!res)
940943
return;
941944
*res = mbus_state.pcie_mem_aperture;
942945
}
946+
EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_mem_aperture);
943947

944948
void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
945949
{
946950
if (!res)
947951
return;
948952
*res = mbus_state.pcie_io_aperture;
949953
}
954+
EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_io_aperture);
950955

951956
int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
952957
{

‎drivers/pci/controller/Kconfig‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ menu "PCI controller drivers"
44
depends on PCI
55

66
config PCI_MVEBU
7-
bool "Marvell EBU PCIe controller"
7+
tristate "Marvell EBU PCIe controller"
88
depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST
99
depends on MVEBU_MBUS
1010
depends on ARM

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