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Hawking Zhangalexdeucher
Hawking Zhang
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alexdeucher
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drm/amdgpu/gfx11: switch to amdgpu_gfx_rlc_init_microcode
switch to common helper to initialize rlc firmware for gfx11 Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 4 additions & 152 deletions
Original file line numberDiff line numberDiff line change
@@ -474,54 +474,6 @@ static void gfx_v11_0_free_microcode(struct amdgpu_device *adev)
474474
kfree(adev->gfx.rlc.register_list_format);
475475
}
476476

477-
static void gfx_v11_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
478-
{
479-
const struct rlc_firmware_header_v2_1 *rlc_hdr;
480-
481-
rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
482-
adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
483-
adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
484-
adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
485-
adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
486-
adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
487-
adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
488-
adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
489-
adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
490-
adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
491-
adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
492-
adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
493-
adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
494-
adev->gfx.rlc.reg_list_format_direct_reg_list_length =
495-
le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
496-
}
497-
498-
static void gfx_v11_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
499-
{
500-
const struct rlc_firmware_header_v2_2 *rlc_hdr;
501-
502-
rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
503-
adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
504-
adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
505-
adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
506-
adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
507-
}
508-
509-
static void gfx_v11_0_init_rlcp_rlcv_microcode(struct amdgpu_device *adev)
510-
{
511-
const struct rlc_firmware_header_v2_3 *rlc_hdr;
512-
513-
rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
514-
adev->gfx.rlcp_ucode_version = le32_to_cpu(rlc_hdr->rlcp_ucode_version);
515-
adev->gfx.rlcp_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcp_ucode_feature_version);
516-
adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes);
517-
adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes);
518-
519-
adev->gfx.rlcv_ucode_version = le32_to_cpu(rlc_hdr->rlcv_ucode_version);
520-
adev->gfx.rlcv_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcv_ucode_feature_version);
521-
adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes);
522-
adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes);
523-
}
524-
525477
static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
526478
{
527479
char fw_name[40];
@@ -532,8 +484,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
532484
const struct gfx_firmware_header_v1_0 *cp_hdr;
533485
const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
534486
const struct rlc_firmware_header_v2_0 *rlc_hdr;
535-
unsigned int *tmp = NULL;
536-
unsigned int i = 0;
537487
uint16_t version_major;
538488
uint16_t version_minor;
539489

@@ -588,58 +538,14 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
588538
if (err)
589539
goto out;
590540
err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
541+
if (err)
542+
goto out;
591543
rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
592544
version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
593545
version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
594-
595-
adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
596-
adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
597-
adev->gfx.rlc.save_and_restore_offset =
598-
le32_to_cpu(rlc_hdr->save_and_restore_offset);
599-
adev->gfx.rlc.clear_state_descriptor_offset =
600-
le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
601-
adev->gfx.rlc.avail_scratch_ram_locations =
602-
le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
603-
adev->gfx.rlc.reg_restore_list_size =
604-
le32_to_cpu(rlc_hdr->reg_restore_list_size);
605-
adev->gfx.rlc.reg_list_format_start =
606-
le32_to_cpu(rlc_hdr->reg_list_format_start);
607-
adev->gfx.rlc.reg_list_format_separate_start =
608-
le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
609-
adev->gfx.rlc.starting_offsets_start =
610-
le32_to_cpu(rlc_hdr->starting_offsets_start);
611-
adev->gfx.rlc.reg_list_format_size_bytes =
612-
le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
613-
adev->gfx.rlc.reg_list_size_bytes =
614-
le32_to_cpu(rlc_hdr->reg_list_size_bytes);
615-
adev->gfx.rlc.register_list_format =
616-
kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
617-
adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
618-
if (!adev->gfx.rlc.register_list_format) {
619-
err = -ENOMEM;
546+
err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
547+
if (err)
620548
goto out;
621-
}
622-
623-
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
624-
le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
625-
for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
626-
adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
627-
628-
adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
629-
630-
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
631-
le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
632-
for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
633-
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
634-
635-
if (version_major == 2) {
636-
if (version_minor >= 1)
637-
gfx_v11_0_init_rlc_ext_microcode(adev);
638-
if (version_minor >= 2)
639-
gfx_v11_0_init_rlc_iram_dram_microcode(adev);
640-
if (version_minor == 3)
641-
gfx_v11_0_init_rlcp_rlcv_microcode(adev);
642-
}
643549
}
644550

645551
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix);
@@ -774,60 +680,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
774680
adev->firmware.fw_size +=
775681
ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
776682
}
777-
778-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
779-
info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
780-
info->fw = adev->gfx.rlc_fw;
781-
if (info->fw) {
782-
header = (const struct common_firmware_header *)info->fw->data;
783-
adev->firmware.fw_size +=
784-
ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
785-
}
786-
if (adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
787-
adev->gfx.rlc.save_restore_list_srm_size_bytes) {
788-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
789-
info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
790-
info->fw = adev->gfx.rlc_fw;
791-
adev->firmware.fw_size +=
792-
ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
793-
794-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
795-
info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
796-
info->fw = adev->gfx.rlc_fw;
797-
adev->firmware.fw_size +=
798-
ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
799-
}
800-
801-
if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
802-
adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
803-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
804-
info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
805-
info->fw = adev->gfx.rlc_fw;
806-
adev->firmware.fw_size +=
807-
ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
808-
809-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
810-
info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
811-
info->fw = adev->gfx.rlc_fw;
812-
adev->firmware.fw_size +=
813-
ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
814-
}
815-
816-
if (adev->gfx.rlc.rlcp_ucode_size_bytes) {
817-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P];
818-
info->ucode_id = AMDGPU_UCODE_ID_RLC_P;
819-
info->fw = adev->gfx.rlc_fw;
820-
adev->firmware.fw_size +=
821-
ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE);
822-
}
823-
824-
if (adev->gfx.rlc.rlcv_ucode_size_bytes) {
825-
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V];
826-
info->ucode_id = AMDGPU_UCODE_ID_RLC_V;
827-
info->fw = adev->gfx.rlc_fw;
828-
adev->firmware.fw_size +=
829-
ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE);
830-
}
831683
}
832684

833685
out:

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