PCI: xgene: Rename xgene_pcie_port to xgene_pcie

firebolt007 · bjorn-helgaas · commit 24d174a116f6 · 2022-01-03T15:05:28.000-06:00
Rename struct xgene_pcie_port to xgene_pcie to match the convention of <driver>_pcie. No functional change intended. Link: https://lore.kernel.org/r/20211223011054.1227810-22-helgaas@kernel.org Signed-off-by: Fan Fei <ffclaire1224@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Toan Le <toan@os.amperecomputing.com>
diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
@@ -60,7 +60,7 @@
 #define XGENE_PCIE_IP_VER_2		2
 
 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
-struct xgene_pcie_port {
+struct xgene_pcie {
 	struct device_node	*node;
 	struct device		*dev;
 	struct clk		*clk;
@@ -71,12 +71,12 @@ struct xgene_pcie_port {
 	u32			version;
 };
 
-static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
+static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg)
 {
 	return readl(port->csr_base + reg);
 }
 
-static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
+static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val)
 {
 	writel(val, port->csr_base + reg);
 }
@@ -86,15 +86,15 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
 	return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
 }
 
-static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
+static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus)
 {
 	struct pci_config_window *cfg;
 
 	if (acpi_disabled)
-		return (struct xgene_pcie_port *)(bus->sysdata);
+		return (struct xgene_pcie *)(bus->sysdata);
 
 	cfg = bus->sysdata;
-	return (struct xgene_pcie_port *)(cfg->priv);
+	return (struct xgene_pcie *)(cfg->priv);
 }
 
 /*
@@ -103,7 +103,7 @@ static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
  */
 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
 {
-	struct xgene_pcie_port *port = pcie_bus_to_port(bus);
+	struct xgene_pcie *port = pcie_bus_to_port(bus);
 
 	if (bus->number >= (bus->primary + 1))
 		return port->cfg_base + AXI_EP_CFG_ACCESS;
@@ -117,7 +117,7 @@ static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
  */
 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
 {
-	struct xgene_pcie_port *port = pcie_bus_to_port(bus);
+	struct xgene_pcie *port = pcie_bus_to_port(bus);
 	unsigned int b, d, f;
 	u32 rtdid_val = 0;
 
@@ -164,7 +164,7 @@ static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
 				    int where, int size, u32 *val)
 {
-	struct xgene_pcie_port *port = pcie_bus_to_port(bus);
+	struct xgene_pcie *port = pcie_bus_to_port(bus);
 
 	if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
 	    PCIBIOS_SUCCESSFUL)
@@ -227,7 +227,7 @@ static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
 {
 	struct device *dev = cfg->parent;
 	struct acpi_device *adev = to_acpi_device(dev);
-	struct xgene_pcie_port *port;
+	struct xgene_pcie *port;
 	struct resource csr;
 	int ret;
 
@@ -281,7 +281,7 @@ const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
 #endif
 
 #if defined(CONFIG_PCI_XGENE)
-static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
+static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr,
 				  u32 flags, u64 size)
 {
 	u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
@@ -307,7 +307,7 @@ static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
 	return mask;
 }
 
-static void xgene_pcie_linkup(struct xgene_pcie_port *port,
+static void xgene_pcie_linkup(struct xgene_pcie *port,
 			      u32 *lanes, u32 *speed)
 {
 	u32 val32;
@@ -322,7 +322,7 @@ static void xgene_pcie_linkup(struct xgene_pcie_port *port,
 	}
 }
 
-static int xgene_pcie_init_port(struct xgene_pcie_port *port)
+static int xgene_pcie_init_port(struct xgene_pcie *port)
 {
 	struct device *dev = port->dev;
 	int rc;
@@ -342,7 +342,7 @@ static int xgene_pcie_init_port(struct xgene_pcie_port *port)
 	return 0;
 }
 
-static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
+static int xgene_pcie_map_reg(struct xgene_pcie *port,
 			      struct platform_device *pdev)
 {
 	struct device *dev = port->dev;
@@ -362,7 +362,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
 	return 0;
 }
 
-static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
+static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port,
 				    struct resource *res, u32 offset,
 				    u64 cpu_addr, u64 pci_addr)
 {
@@ -394,7 +394,7 @@ static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
 	xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
 }
 
-static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
+static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port)
 {
 	u64 addr = port->cfg_addr;
 
@@ -403,7 +403,7 @@ static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
 	xgene_pcie_writel(port, CFGCTL, EN_REG);
 }
 
-static int xgene_pcie_map_ranges(struct xgene_pcie_port *port)
+static int xgene_pcie_map_ranges(struct xgene_pcie *port)
 {
 	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
 	struct resource_entry *window;
@@ -444,7 +444,7 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port *port)
 	return 0;
 }
 
-static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
+static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg,
 				  u64 pim, u64 size)
 {
 	xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
@@ -478,7 +478,7 @@ static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
 	return -EINVAL;
 }
 
-static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
+static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port,
 				    struct resource_entry *entry,
 				    u8 *ib_reg_mask)
 {
@@ -529,7 +529,7 @@ static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
 	xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
 }
 
-static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
+static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port)
 {
 	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
 	struct resource_entry *entry;
@@ -542,15 +542,15 @@ static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
 }
 
 /* clear BAR configuration which was done by firmware */
-static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
+static void xgene_pcie_clear_config(struct xgene_pcie *port)
 {
 	int i;
 
 	for (i = PIM1_1L; i <= CFGCTL; i += 4)
 		xgene_pcie_writel(port, i, 0);
 }
 
-static int xgene_pcie_setup(struct xgene_pcie_port *port)
+static int xgene_pcie_setup(struct xgene_pcie *port)
 {
 	struct device *dev = port->dev;
 	u32 val, lanes = 0, speed = 0;
@@ -588,7 +588,7 @@ static int xgene_pcie_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *dn = dev->of_node;
-	struct xgene_pcie_port *port;
+	struct xgene_pcie *port;
 	struct pci_host_bridge *bridge;
 	int ret;
 

Original file line number	Diff line number	Diff line change
`@@ -60,7 +60,7 @@`
`60`	`60`	`#define XGENE_PCIE_IP_VER_2 2`
`61`	`61`
`62`	`62`	`#if defined(CONFIG_PCI_XGENE) \|\| (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))`
`63`		`-struct xgene_pcie_port {`
	`63`	`+struct xgene_pcie {`
`64`	`64`	`struct device_node *node;`
`65`	`65`	`struct device *dev;`
`66`	`66`	`struct clk *clk;`
`@@ -71,12 +71,12 @@ struct xgene_pcie_port {`
`71`	`71`	`u32 version;`
`72`	`72`	`};`
`73`	`73`
`74`		`-static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)`
	`74`	`+static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg)`
`75`	`75`	`{`
`76`	`76`	`return readl(port->csr_base + reg);`
`77`	`77`	`}`
`78`	`78`
`79`		`-static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)`
	`79`	`+static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val)`
`80`	`80`	`{`
`81`	`81`	`writel(val, port->csr_base + reg);`
`82`	`82`	`}`
`@@ -86,15 +86,15 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)`
`86`	`86`	`return (addr & PCI_BASE_ADDRESS_MEM_MASK) \| flags;`
`87`	`87`	`}`
`88`	`88`
`89`		`-static inline struct xgene_pcie_port pcie_bus_to_port(struct pci_bus bus)`
	`89`	`+static inline struct xgene_pcie pcie_bus_to_port(struct pci_bus bus)`
`90`	`90`	`{`
`91`	`91`	`struct pci_config_window *cfg;`
`92`	`92`
`93`	`93`	`if (acpi_disabled)`
`94`		`- return (struct xgene_pcie_port *)(bus->sysdata);`
	`94`	`+ return (struct xgene_pcie *)(bus->sysdata);`
`95`	`95`
`96`	`96`	`cfg = bus->sysdata;`
`97`		`- return (struct xgene_pcie_port *)(cfg->priv);`
	`97`	`+ return (struct xgene_pcie *)(cfg->priv);`
`98`	`98`	`}`
`99`	`99`
`100`	`100`	`/*`
`@@ -103,7 +103,7 @@ static inline struct xgene_pcie_port pcie_bus_to_port(struct pci_bus bus)`
`103`	`103`	`*/`
`104`	`104`	`static void __iomem xgene_pcie_get_cfg_base(struct pci_bus bus)`
`105`	`105`	`{`
`106`		`- struct xgene_pcie_port *port = pcie_bus_to_port(bus);`
	`106`	`+ struct xgene_pcie *port = pcie_bus_to_port(bus);`
`107`	`107`
`108`	`108`	`if (bus->number >= (bus->primary + 1))`
`109`	`109`	`return port->cfg_base + AXI_EP_CFG_ACCESS;`
`@@ -117,7 +117,7 @@ static void __iomem xgene_pcie_get_cfg_base(struct pci_bus bus)`
`117`	`117`	`*/`
`118`	`118`	`static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)`
`119`	`119`	`{`
`120`		`- struct xgene_pcie_port *port = pcie_bus_to_port(bus);`
	`120`	`+ struct xgene_pcie *port = pcie_bus_to_port(bus);`
`121`	`121`	`unsigned int b, d, f;`
`122`	`122`	`u32 rtdid_val = 0;`
`123`	`123`
`@@ -164,7 +164,7 @@ static void __iomem xgene_pcie_map_bus(struct pci_bus bus, unsigned int devfn,`
`164`	`164`	`static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,`
`165`	`165`	`int where, int size, u32 *val)`
`166`	`166`	`{`
`167`		`- struct xgene_pcie_port *port = pcie_bus_to_port(bus);`
	`167`	`+ struct xgene_pcie *port = pcie_bus_to_port(bus);`
`168`	`168`
`169`	`169`	`if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=`
`170`	`170`	`PCIBIOS_SUCCESSFUL)`
`@@ -227,7 +227,7 @@ static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)`
`227`	`227`	`{`
`228`	`228`	`struct device *dev = cfg->parent;`
`229`	`229`	`struct acpi_device *adev = to_acpi_device(dev);`
`230`		`- struct xgene_pcie_port *port;`
	`230`	`+ struct xgene_pcie *port;`
`231`	`231`	`struct resource csr;`
`232`	`232`	`int ret;`
`233`	`233`
`@@ -281,7 +281,7 @@ const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {`
`281`	`281`	`#endif`
`282`	`282`
`283`	`283`	`#if defined(CONFIG_PCI_XGENE)`
`284`		`-static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,`
	`284`	`+static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr,`
`285`	`285`	`u32 flags, u64 size)`
`286`	`286`	`{`
`287`	`287`	`u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) \| flags;`
`@@ -307,7 +307,7 @@ static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,`
`307`	`307`	`return mask;`
`308`	`308`	`}`
`309`	`309`
`310`		`-static void xgene_pcie_linkup(struct xgene_pcie_port *port,`
	`310`	`+static void xgene_pcie_linkup(struct xgene_pcie *port,`
`311`	`311`	`u32 lanes, u32 speed)`
`312`	`312`	`{`
`313`	`313`	`u32 val32;`
`@@ -322,7 +322,7 @@ static void xgene_pcie_linkup(struct xgene_pcie_port *port,`
`322`	`322`	`}`
`323`	`323`	`}`
`324`	`324`
`325`		`-static int xgene_pcie_init_port(struct xgene_pcie_port *port)`
	`325`	`+static int xgene_pcie_init_port(struct xgene_pcie *port)`
`326`	`326`	`{`
`327`	`327`	`struct device *dev = port->dev;`
`328`	`328`	`int rc;`
`@@ -342,7 +342,7 @@ static int xgene_pcie_init_port(struct xgene_pcie_port *port)`
`342`	`342`	`return 0;`
`343`	`343`	`}`
`344`	`344`
`345`		`-static int xgene_pcie_map_reg(struct xgene_pcie_port *port,`
	`345`	`+static int xgene_pcie_map_reg(struct xgene_pcie *port,`
`346`	`346`	`struct platform_device *pdev)`
`347`	`347`	`{`
`348`	`348`	`struct device *dev = port->dev;`
`@@ -362,7 +362,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,`
`362`	`362`	`return 0;`
`363`	`363`	`}`
`364`	`364`
`365`		`-static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,`
	`365`	`+static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port,`
`366`	`366`	`struct resource *res, u32 offset,`
`367`	`367`	`u64 cpu_addr, u64 pci_addr)`
`368`	`368`	`{`
`@@ -394,7 +394,7 @@ static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,`
`394`	`394`	`xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));`
`395`	`395`	`}`
`396`	`396`
`397`		`-static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)`
	`397`	`+static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port)`
`398`	`398`	`{`
`399`	`399`	`u64 addr = port->cfg_addr;`
`400`	`400`
`@@ -403,7 +403,7 @@ static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)`
`403`	`403`	`xgene_pcie_writel(port, CFGCTL, EN_REG);`
`404`	`404`	`}`
`405`	`405`
`406`		`-static int xgene_pcie_map_ranges(struct xgene_pcie_port *port)`
	`406`	`+static int xgene_pcie_map_ranges(struct xgene_pcie *port)`
`407`	`407`	`{`
`408`	`408`	`struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);`
`409`	`409`	`struct resource_entry *window;`
`@@ -444,7 +444,7 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port *port)`
`444`	`444`	`return 0;`
`445`	`445`	`}`
`446`	`446`
`447`		`-static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,`
	`447`	`+static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg,`
`448`	`448`	`u64 pim, u64 size)`
`449`	`449`	`{`
`450`	`450`	`xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));`
`@@ -478,7 +478,7 @@ static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)`
`478`	`478`	`return -EINVAL;`
`479`	`479`	`}`
`480`	`480`
`481`		`-static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,`
	`481`	`+static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port,`
`482`	`482`	`struct resource_entry *entry,`
`483`	`483`	`u8 *ib_reg_mask)`
`484`	`484`	`{`
`@@ -529,7 +529,7 @@ static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,`
`529`	`529`	`xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));`
`530`	`530`	`}`
`531`	`531`
`532`		`-static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)`
	`532`	`+static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port)`
`533`	`533`	`{`
`534`	`534`	`struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);`
`535`	`535`	`struct resource_entry *entry;`
`@@ -542,15 +542,15 @@ static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)`
`542`	`542`	`}`
`543`	`543`
`544`	`544`	`/* clear BAR configuration which was done by firmware */`
`545`		`-static void xgene_pcie_clear_config(struct xgene_pcie_port *port)`
	`545`	`+static void xgene_pcie_clear_config(struct xgene_pcie *port)`
`546`	`546`	`{`
`547`	`547`	`int i;`
`548`	`548`
`549`	`549`	`for (i = PIM1_1L; i <= CFGCTL; i += 4)`
`550`	`550`	`xgene_pcie_writel(port, i, 0);`
`551`	`551`	`}`
`552`	`552`
`553`		`-static int xgene_pcie_setup(struct xgene_pcie_port *port)`
	`553`	`+static int xgene_pcie_setup(struct xgene_pcie *port)`
`554`	`554`	`{`
`555`	`555`	`struct device *dev = port->dev;`
`556`	`556`	`u32 val, lanes = 0, speed = 0;`
`@@ -588,7 +588,7 @@ static int xgene_pcie_probe(struct platform_device *pdev)`
`588`	`588`	`{`
`589`	`589`	`struct device *dev = &pdev->dev;`
`590`	`590`	`struct device_node *dn = dev->of_node;`
`591`		`- struct xgene_pcie_port *port;`
	`591`	`+ struct xgene_pcie *port;`
`592`	`592`	`struct pci_host_bridge *bridge;`
`593`	`593`	`int ret;`
`594`	`594`