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Merge branch 'remotes/lorenzo/pci/dwc'
- Fix n_fts[] array overrun (Vidya Sagar) - Don't advertise PTM Responder role for Endpoints (Vidya Sagar) - Fix qcom "reset assert" error message (Manivannan Sadhasivam) - Downgrade "link didn't come up" message to dev_info (Vidya Sagar) - Initialize PHY before deasserting core reset so the link comes up on boards where the PHY provides the reference clock (this was a regression in v6.0) (Sascha Hauer) - Switch histb to the gpiod API (Dmitry Torokhov) - Fix imx6sx and imx8mq clock names in DT binding (Serge Semin) - Fix visconti MSI interrupt in DT binding (Serge Semin) - Consolidate reset-gpio, cdm, windows info in common DT shared by both Root Port and Endpoint bindings (Serge Semin) - Remove bus node from DT examples (Serge Semin) - Add common phys, phy-names to DT (Serge Semin) - Add default max-link-speed of Gen5 to DT (Serge Semin) - Apply generic schema for generic device (Serge Semin) - Add default max-functions of 32 to DT (Serge Semin) - Add common interrupts, interrupt-names to DT (Serge Semin) - Add common regs, reg-names to DT (Serge Semin) - Add common clocks, resets to DT (Serge Semin) - Add dma-coherent to DT (Serge Semin) - Apply common schema to Rockchip DT (Serge Semin) - Add Baikal-T1 DT bindings (Serge Semin) - Add dma-ranges support in DesignWare core (Serge Semin) - Add dw_pcie_cap_is() for testing controller capabilities (Serge Semin) - Add generic resources getter to DesignWare core (Serge Semin) - Combine iATU detection procedures (Serge Semin) - Add generic clock and reset names to DesignWare core (Serge Semin) - Add Baikal-T1 PCIe controller driver (Serge Semin) * remotes/lorenzo/pci/dwc: PCI: dwc: Add Baikal-T1 PCIe controller support PCI: dwc: Introduce generic platform clocks and resets PCI: dwc: Combine iATU detection procedures PCI: dwc: Introduce generic resources getter PCI: dwc: Introduce generic controller capabilities interface PCI: dwc: Introduce dma-ranges property support for RC-host dt-bindings: PCI: dwc: Add Baikal-T1 PCIe Root Port bindings dt-bindings: PCI: dwc: Apply common schema to Rockchip DW PCIe nodes dt-bindings: PCI: dwc: Add dma-coherent property dt-bindings: PCI: dwc: Add clocks/resets common properties dt-bindings: PCI: dwc: Add reg/reg-names common properties dt-bindings: PCI: dwc: Add interrupts/interrupt-names common properties dt-bindings: PCI: dwc: Add max-functions EP property dt-bindings: PCI: dwc: Apply generic schema for generic device only dt-bindings: PCI: dwc: Add max-link-speed common property dt-bindings: PCI: dwc: Add phys/phy-names common properties dt-bindings: PCI: dwc: Remove bus node from the examples dt-bindings: PCI: dwc: Detach common RP/EP DT bindings dt-bindings: visconti-pcie: Fix interrupts array max constraints dt-bindings: imx6q-pcie: Fix clock names for imx6sx and imx8mq PCI: histb: Switch to using gpiod API PCI: imx6: Initialize PHY before deasserting core reset PCI: dwc: Use dev_info for PCIe link down event logging PCI: qcom: Fix error message for reset_control_assert() PCI: designware-ep: Disable PTM capabilities for EP mode PCI: Add PCI_PTM_CAP_RES macro PCI: dwc: Fix n_fts[] array overrun
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‎Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Baikal-T1 PCIe Root Port Controller
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maintainers:
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- Serge Semin <[email protected]>
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description:
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Embedded into Baikal-T1 SoC Root Complex controller with a single port
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activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
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to have just a single Root Port function and is capable of establishing the
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link up to Gen.3 speed on x4 lanes. It doesn't have embedded clock and reset
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control module, so the proper interface initialization is supposed to be
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performed by software. There four in- and four outbound iATU regions
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which can be used to emit all required TLP types on the PCIe bus.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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const: baikal,bt1-pcie
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reg:
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description:
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DBI, DBI2 and at least 4KB outbound iATU-capable region for the
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peripheral devices CFG-space access.
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maxItems: 3
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: config
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interrupts:
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description:
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MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization
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request and eight Read/Write eDMA IRQ lines are available.
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maxItems: 14
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interrupt-names:
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items:
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- const: dma0
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- const: dma1
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- const: dma2
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- const: dma3
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- const: dma4
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- const: dma5
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- const: dma6
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- const: dma7
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- const: msi
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- const: aer
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- const: pme
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- const: hp
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- const: bw_mg
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- const: l_eq
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clocks:
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description:
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DBI (attached to the APB bus), AXI-bus master and slave interfaces
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are fed up by the dedicated application clocks. A common reference
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clock signal is supposed to be attached to the corresponding Ref-pad
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of the SoC. It will be redistributed amongst the controller core
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sub-modules (pipe, core, aux, etc).
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maxItems: 4
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clock-names:
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items:
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- const: dbi
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- const: mstr
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- const: slv
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- const: ref
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resets:
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description:
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A comprehensive controller reset logic is supposed to be implemented
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by software, so almost all the possible application and core reset
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signals are exposed via the system CCU module.
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maxItems: 9
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reset-names:
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items:
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- const: mstr
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- const: slv
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- const: pwr
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- const: hot
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- const: phy
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- const: core
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- const: pipe
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- const: sticky
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- const: non-sticky
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baikal,bt1-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the Baikal-T1 System Controller DT node. It's required to
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access some additional PM, Reset-related and LTSSM signals.
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num-lanes:
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maximum: 4
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max-link-speed:
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maximum: 3
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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pcie@1f052000 {
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compatible = "baikal,bt1-pcie";
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device_type = "pci";
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reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>;
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reg-names = "dbi", "dbi2", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>,
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<0x82000000 0 0x20000000 0x08000000 0 0x13db0000>;
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bus-range = <0x0 0xff>;
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interrupts = <GIC_SHARED 80 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 81 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 82 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SHARED 93 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma0", "dma1", "dma2", "dma3",
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"dma4", "dma5", "dma6", "dma7",
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"msi", "aer", "pme", "hp", "bw_mg",
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"l_eq";
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clocks = <&ccu_sys 1>, <&ccu_axi 6>, <&ccu_axi 7>, <&clk_pcie>;
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clock-names = "dbi", "mstr", "slv", "ref";
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resets = <&ccu_axi 6>, <&ccu_axi 7>, <&ccu_sys 7>, <&ccu_sys 10>,
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<&ccu_sys 4>, <&ccu_sys 6>, <&ccu_sys 5>, <&ccu_sys 8>,
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<&ccu_sys 9>;
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reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe",
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"sticky", "non-sticky";
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reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>;
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num-lanes = <4>;
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max-link-speed = <3>;
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};
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...

‎Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml‎

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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in snps,dw-pcie.yaml.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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enum:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
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- enum: [ pcie_inbound_axi, pcie_aux ]
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num-lanes:
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const: 1
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- clocks
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- clock-names
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx6sx-pcie
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then:
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properties:
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clock-names:
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items:
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- {}
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- {}
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- {}
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- const: pcie_inbound_axi
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8mq-pcie
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then:
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properties:
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clock-names:
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items:
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- {}
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- {}
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- {}
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- const: pcie_aux
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- if:
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properties:
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compatible:
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not:
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contains:
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enum:
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- fsl,imx6sx-pcie
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- fsl,imx8mq-pcie
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then:
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properties:
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clock-names:
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maxItems: 3
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unevaluatedProperties: false
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examples:

‎Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml‎

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description: |+
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RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
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PCIe IP and thus inherits all the common properties defined in
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designware-pcie.txt.
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snps,dw-pcie.yaml.
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:

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