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airliedairlied
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Merge tag 'amd-drm-fixes-6.2-2023-02-08' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.2-2023-02-08: amdgpu: - Flickering fixes for DCN 2.1, 3.1.2/3 - Re-enable S/G display on DCN 3.1.4 - Properly fix S/G display with AGP aperture enabled - Fix cursor offset with 180 rotation - SMU13 fixes - Use TGID for GPUVM traces - Fix oops on in fence error path - Don't run IB tests on hw rings when sw rings are in use Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 04119ab + c6ac406 commit 4684f5c

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+71
-41
lines changed

13 files changed

+71
-41
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -618,7 +618,13 @@ void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
618618
if (!ring || !ring->fence_drv.initialized)
619619
continue;
620620

621-
if (!ring->no_scheduler)
621+
/*
622+
* Notice we check for sched.ops since there's some
623+
* override on the meaning of sched.ready by amdgpu.
624+
* The natural check would be sched.ready, which is
625+
* set as drm_sched_init() finishes...
626+
*/
627+
if (ring->sched.ops)
622628
drm_sched_fini(&ring->sched);
623629

624630
for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -295,7 +295,7 @@ struct amdgpu_ring {
295295
#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
296296
#define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))
297297
#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
298-
#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
298+
#define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
299299
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
300300
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
301301
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -974,7 +974,7 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
974974
trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
975975
min(nptes, 32u), dst, incr,
976976
upd_flags,
977-
vm->task_info.pid,
977+
vm->task_info.tgid,
978978
vm->immediate.fence_context);
979979
amdgpu_vm_pte_update_flags(params, to_amdgpu_bo_vm(pt),
980980
cursor.level, pe_start, dst,

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6877,7 +6877,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
68776877
.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
68786878
.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
68796879
.test_ring = gfx_v9_0_ring_test_ring,
6880-
.test_ib = gfx_v9_0_ring_test_ib,
68816880
.insert_nop = amdgpu_ring_insert_nop,
68826881
.pad_ib = amdgpu_ring_generic_pad_ib,
68836882
.emit_switch_buffer = gfx_v9_ring_emit_sb,

‎drivers/gpu/drm/amd/amdgpu/soc21.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -641,7 +641,9 @@ static int soc21_common_early_init(void *handle)
641641
AMD_CG_SUPPORT_GFX_CGLS |
642642
AMD_CG_SUPPORT_REPEATER_FGCG |
643643
AMD_CG_SUPPORT_GFX_MGCG |
644-
AMD_CG_SUPPORT_HDP_SD;
644+
AMD_CG_SUPPORT_HDP_SD |
645+
AMD_CG_SUPPORT_ATHUB_MGCG |
646+
AMD_CG_SUPPORT_ATHUB_LS;
645647
adev->pg_flags = AMD_PG_SUPPORT_VCN |
646648
AMD_PG_SUPPORT_VCN_DPG |
647649
AMD_PG_SUPPORT_JPEG;

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c‎

Lines changed: 29 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1184,24 +1184,38 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
11841184

11851185
memset(pa_config, 0, sizeof(*pa_config));
11861186

1187-
logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1188-
pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1189-
1190-
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1191-
/*
1192-
* Raven2 has a HW issue that it is unable to use the vram which
1193-
* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1194-
* workaround that increase system aperture high address (add 1)
1195-
* to get rid of the VM fault and hardware hang.
1196-
*/
1197-
logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1198-
else
1199-
logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1200-
12011187
agp_base = 0;
12021188
agp_bot = adev->gmc.agp_start >> 24;
12031189
agp_top = adev->gmc.agp_end >> 24;
12041190

1191+
/* AGP aperture is disabled */
1192+
if (agp_bot == agp_top) {
1193+
logical_addr_low = adev->gmc.vram_start >> 18;
1194+
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1195+
/*
1196+
* Raven2 has a HW issue that it is unable to use the vram which
1197+
* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1198+
* workaround that increase system aperture high address (add 1)
1199+
* to get rid of the VM fault and hardware hang.
1200+
*/
1201+
logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1202+
else
1203+
logical_addr_high = adev->gmc.vram_end >> 18;
1204+
} else {
1205+
logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1206+
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1207+
/*
1208+
* Raven2 has a HW issue that it is unable to use the vram which
1209+
* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1210+
* workaround that increase system aperture high address (add 1)
1211+
* to get rid of the VM fault and hardware hang.
1212+
*/
1213+
logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1214+
else
1215+
logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1216+
}
1217+
1218+
pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
12051219

12061220
page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
12071221
page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
@@ -1499,10 +1513,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
14991513
(adev->apu_flags & AMD_APU_IS_PICASSO))
15001514
init_data.flags.gpu_vm_support = true;
15011515
break;
1502-
case IP_VERSION(2, 1, 0):
15031516
case IP_VERSION(3, 0, 1):
1504-
case IP_VERSION(3, 1, 2):
1505-
case IP_VERSION(3, 1, 3):
1517+
case IP_VERSION(3, 1, 4):
15061518
case IP_VERSION(3, 1, 6):
15071519
init_data.flags.gpu_vm_support = true;
15081520
break;

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3626,7 +3626,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
36263626
(int)hubp->curs_attr.width || pos_cpy.x
36273627
<= (int)hubp->curs_attr.width +
36283628
pipe_ctx->plane_state->src_rect.x) {
3629-
pos_cpy.x = temp_x + viewport_width;
3629+
pos_cpy.x = 2 * viewport_width - temp_x;
36303630
}
36313631
}
36323632
} else {

‎drivers/gpu/drm/amd/pm/amdgpu_pm.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1991,6 +1991,8 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
19911991
case IP_VERSION(9, 4, 2):
19921992
case IP_VERSION(10, 3, 0):
19931993
case IP_VERSION(11, 0, 0):
1994+
case IP_VERSION(11, 0, 1):
1995+
case IP_VERSION(11, 0, 2):
19941996
*states = ATTR_STATE_SUPPORTED;
19951997
break;
19961998
default:

‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,8 @@
123123
(1 << FEATURE_DS_FCLK_BIT) | \
124124
(1 << FEATURE_DS_LCLK_BIT) | \
125125
(1 << FEATURE_DS_DCFCLK_BIT) | \
126-
(1 << FEATURE_DS_UCLK_BIT))
126+
(1 << FEATURE_DS_UCLK_BIT) | \
127+
(1ULL << FEATURE_DS_VCN_BIT))
127128

128129
//For use with feature control messages
129130
typedef enum {
@@ -522,9 +523,9 @@ typedef enum {
522523
TEMP_HOTSPOT_M,
523524
TEMP_MEM,
524525
TEMP_VR_GFX,
525-
TEMP_VR_SOC,
526526
TEMP_VR_MEM0,
527527
TEMP_VR_MEM1,
528+
TEMP_VR_SOC,
528529
TEMP_VR_U,
529530
TEMP_LIQUID0,
530531
TEMP_LIQUID1,

‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h‎

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -113,20 +113,21 @@
113113
#define NUM_FEATURES 64
114114

115115
#define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL
116-
#define ALLOWED_FEATURE_CTRL_SCPM (1 << FEATURE_DPM_GFXCLK_BIT) | \
117-
(1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
118-
(1 << FEATURE_DPM_UCLK_BIT) | \
119-
(1 << FEATURE_DPM_FCLK_BIT) | \
120-
(1 << FEATURE_DPM_SOCCLK_BIT) | \
121-
(1 << FEATURE_DPM_MP0CLK_BIT) | \
122-
(1 << FEATURE_DPM_LINK_BIT) | \
123-
(1 << FEATURE_DPM_DCN_BIT) | \
124-
(1 << FEATURE_DS_GFXCLK_BIT) | \
125-
(1 << FEATURE_DS_SOCCLK_BIT) | \
126-
(1 << FEATURE_DS_FCLK_BIT) | \
127-
(1 << FEATURE_DS_LCLK_BIT) | \
128-
(1 << FEATURE_DS_DCFCLK_BIT) | \
129-
(1 << FEATURE_DS_UCLK_BIT)
116+
#define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \
117+
(1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
118+
(1 << FEATURE_DPM_UCLK_BIT) | \
119+
(1 << FEATURE_DPM_FCLK_BIT) | \
120+
(1 << FEATURE_DPM_SOCCLK_BIT) | \
121+
(1 << FEATURE_DPM_MP0CLK_BIT) | \
122+
(1 << FEATURE_DPM_LINK_BIT) | \
123+
(1 << FEATURE_DPM_DCN_BIT) | \
124+
(1 << FEATURE_DS_GFXCLK_BIT) | \
125+
(1 << FEATURE_DS_SOCCLK_BIT) | \
126+
(1 << FEATURE_DS_FCLK_BIT) | \
127+
(1 << FEATURE_DS_LCLK_BIT) | \
128+
(1 << FEATURE_DS_DCFCLK_BIT) | \
129+
(1 << FEATURE_DS_UCLK_BIT) | \
130+
(1ULL << FEATURE_DS_VCN_BIT))
130131

131132
//For use with feature control messages
132133
typedef enum {

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