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perf vendor events intel: Refresh meteorlake events
Update the meteorlake events using the new tooling from: https://github.com/intel/perfmon The events are unchanged but they are sorted and unused json values are removed. This increases consistency across the json files. The CPUID matching regular expression is updated to match the perfmon one. Signed-off-by: Ian Rogers <[email protected]> Acked-by: Kan Liang <[email protected]> Cc: Adrian Hunter <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Caleb Biggers <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: John Garry <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Perry Taylor <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Xing Zhengjun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
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‎tools/perf/pmu-events/arch/x86/mapfile.csv‎

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@@ -17,7 +17,7 @@ GenuineIntel-6-3A,v23,ivybridge,core
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GenuineIntel-6-3E,v22,ivytown,core
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GenuineIntel-6-2D,v21,jaketown,core
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GenuineIntel-6-(57|85),v9,knightslanding,core
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GenuineIntel-6-AA,v1.00,meteorlake,core
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GenuineIntel-6-A[AC],v1.00,meteorlake,core
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GenuineIntel-6-1[AEF],v3,nehalemep,core
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GenuineIntel-6-2E,v3,nehalemex,core
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GenuineIntel-6-2A,v17,sandybridge,core

‎tools/perf/pmu-events/arch/x86/meteorlake/cache.json‎

Lines changed: 52 additions & 118 deletions
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@@ -1,262 +1,196 @@
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[
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{
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"BriefDescription": "L2 code requests",
4+
"EventCode": "0x24",
5+
"EventName": "L2_RQSTS.ALL_CODE_RD",
6+
"SampleAfterValue": "200003",
7+
"UMask": "0xe4",
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"Unit": "cpu_core"
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},
10+
{
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"BriefDescription": "Demand Data Read access L2 cache",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
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"SampleAfterValue": "200003",
15+
"UMask": "0xe1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
4-
"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.MISS",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"UMask": "0x41",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.MISS",
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"SampleAfterValue": "100003",
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"UMask": "0x41",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
15-
"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.REFERENCE",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"UMask": "0x4f",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.REFERENCE",
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"SampleAfterValue": "100003",
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"UMask": "0x4f",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Retired load instructions.",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_LOADS",
55+
"PEBS": "1",
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"SampleAfterValue": "1000003",
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"UMask": "0x81",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Retired store instructions.",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_STORES",
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"PEBS": "1",
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"SampleAfterValue": "1000003",
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"UMask": "0x82",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of load ops retired.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"UMask": "0x81",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of store ops retired.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"UMask": "0x82",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x80",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x10",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x100",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x20",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x4",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x200",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
148-
"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x40",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
164-
"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x8",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"UMask": "0x6",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "L2 code requests",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.ALL_CODE_RD",
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"PEBScounters": "0,1,2,3",
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"SampleAfterValue": "200003",
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"UMask": "0xe4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Demand Data Read access L2 cache",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
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"PEBScounters": "0,1,2,3",
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"SampleAfterValue": "200003",
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"UMask": "0xe1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
215-
"CollectPEBSRecord": "2",
216-
"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.MISS",
219-
"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "100003",
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"UMask": "0x41",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
229-
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
230-
"PEBScounters": "0,1,2,3,4,5,6,7",
231-
"SampleAfterValue": "100003",
232-
"UMask": "0x4f",
233-
"Unit": "cpu_core"
234-
},
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{
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"BriefDescription": "Retired load instructions.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
239-
"Data_LA": "1",
240-
"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_LOADS",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3",
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"SampleAfterValue": "1000003",
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"UMask": "0x81",
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"Unit": "cpu_core"
247-
},
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{
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"BriefDescription": "Retired store instructions.",
250-
"CollectPEBSRecord": "2",
251-
"Counter": "0,1,2,3",
252-
"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_STORES",
255-
"L1_Hit_Indication": "1",
256-
"PEBS": "1",
257-
"PEBScounters": "0,1,2,3",
258-
"SampleAfterValue": "1000003",
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"UMask": "0x82",
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"Unit": "cpu_core"
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}
262196
]

‎tools/perf/pmu-events/arch/x86/meteorlake/frontend.json‎

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[
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{
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"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
4-
"CollectPEBSRecord": "2",
5-
"Counter": "0,1,2,3,4,5,6,7",
64
"EventCode": "0x80",
75
"EventName": "ICACHE.ACCESSES",
8-
"PEBScounters": "0,1,2,3,4,5,6,7",
96
"SampleAfterValue": "200003",
107
"UMask": "0x3",
118
"Unit": "cpu_atom"
129
},
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{
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"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
15-
"CollectPEBSRecord": "2",
16-
"Counter": "0,1,2,3,4,5,6,7",
1712
"EventCode": "0x80",
1813
"EventName": "ICACHE.MISSES",
19-
"PEBScounters": "0,1,2,3,4,5,6,7",
2014
"SampleAfterValue": "200003",
2115
"UMask": "0x2",
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"Unit": "cpu_atom"

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