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Merge tag 'media/v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab: - New driver for Mediatek MDP V3 - New driver for NXP i.MX DW100 dewarper - Zoran driver got promoted from staging - Hantro and related drivers got promoted from staging - Several VB1 drivers got moved to staging/deprecated (cpia2, fsl-viu, meye, saa7146, av7110, stkwebcam, tm6000, vpfe_capture, davinci, zr364xx) - Usual set of driver fixes, improvements and cleanups * tag 'media/v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (107 commits) media: destage Hantro VPU driver media: platform: mtk-mdp3: add MediaTek MDP3 driver media: dt-binding: mediatek: add bindings for MediaTek CCORR and WDMA media: dt-binding: mediatek: add bindings for MediaTek MDP3 components media: xilinx: vipp: Fix refcount leak in xvip_graph_dma_init media: xilinx: video: Add 1X12 greyscale format media: xilinx: csi2rxss: Add 1X12 greyscale format media: staging: media: imx: imx7-media-csi: Increase video mem limit media: uvcvideo: Limit power line control for Sonix Technology media: uvcvideo: Use entity get_cur in uvc_ctrl_set media: uvcvideo: Fix typo 'the the' in comment media: uvcvideo: Use indexed loops in uvc_ctrl_init_ctrl() media: uvcvideo: Fix memory leak in uvc_gpio_parse media: renesas: vsp1: Add support for RZ/G2L VSPD media: renesas: vsp1: Add VSP1_HAS_NON_ZERO_LBA feature bit media: renesas: vsp1: Add support for VSP software version media: renesas: vsp1: Add support to deassert/assert reset line media: dt-bindings: media: renesas,vsp1: Document RZ/G2L VSPD bindings media: meson: vdec: add missing clk_disable_unprepare on error in vdec_hevc_start() media: amphion: fix a bug that vpu core may not resume after suspend ...
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‎Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Read Direct Memory Access
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maintainers:
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- Matthias Brugger <[email protected]>
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- Moudy Ho <[email protected]>
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description: |
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MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
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It contains one line buffer to store the sufficient pixel data, and
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must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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properties:
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compatible:
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items:
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- const: mediatek,mt8183-mdp3-rdma
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reg:
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maxItems: 1
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mediatek,gce-client-reg:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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items:
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items:
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- description: phandle of GCE
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- description: GCE subsys id
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- description: register offset
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- description: register size
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property. Each GCE subsys id is mapping to
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a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
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mediatek,gce-events:
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description:
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The event id which is mapping to the specific hardware event signal
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to gce. The event id is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h of each chips.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: RDMA clock
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- description: RSZ clock
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iommus:
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maxItems: 1
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mboxes:
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items:
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- description: used for 1st data pipe from RDMA
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- description: used for 2nd data pipe from RDMA
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required:
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- compatible
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- reg
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- mediatek,gce-client-reg
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- mediatek,gce-events
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- power-domains
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- clocks
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- iommus
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- mboxes
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/gce/mt8183-gce.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/memory/mt8183-larb-port.h>
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mdp3_rdma0: mdp3-rdma0@14001000 {
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compatible = "mediatek,mt8183-mdp3-rdma";
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reg = <0x14001000 0x1000>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
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mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
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<CMDQ_EVENT_MDP_RDMA0_EOF>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_MDP_RDMA0>,
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<&mmsys CLK_MM_MDP_RSZ1>;
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iommus = <&iommu>;
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mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
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<&gce 21 CMDQ_THR_PRIO_LOWEST>;
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};

‎Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Resizer
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maintainers:
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- Matthias Brugger <[email protected]>
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- Moudy Ho <[email protected]>
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description: |
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One of Media Data Path 3 (MDP3) components used to do frame resizing.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8183-mdp3-rsz
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reg:
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maxItems: 1
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mediatek,gce-client-reg:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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items:
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- description: phandle of GCE
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- description: GCE subsys id
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- description: register offset
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- description: register size
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property. Each GCE subsys id is mapping to
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a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
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mediatek,gce-events:
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description:
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The event id which is mapping to the specific hardware event signal
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to gce. The event id is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h of each chips.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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clocks:
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minItems: 1
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required:
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- compatible
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- reg
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- mediatek,gce-client-reg
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- mediatek,gce-events
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/gce/mt8183-gce.h>
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mdp3_rsz0: mdp3-rsz0@14003000 {
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compatible = "mediatek,mt8183-mdp3-rsz";
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reg = <0x14003000 0x1000>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
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mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
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<CMDQ_EVENT_MDP_RSZ0_EOF>;
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clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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};
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mdp3_rsz1: mdp3-rsz1@14004000 {
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compatible = "mediatek,mt8183-mdp3-rsz";
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reg = <0x14004000 0x1000>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
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mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
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<CMDQ_EVENT_MDP_RSZ1_EOF>;
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clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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};

‎Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Write DMA with Rotation
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maintainers:
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- Matthias Brugger <[email protected]>
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- Moudy Ho <[email protected]>
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description: |
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One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8183-mdp3-wrot
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reg:
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maxItems: 1
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mediatek,gce-client-reg:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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items:
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- description: phandle of GCE
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- description: GCE subsys id
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- description: register offset
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- description: register size
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property. Each GCE subsys id is mapping to
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a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
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mediatek,gce-events:
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description:
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The event id which is mapping to the specific hardware event signal
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to gce. The event id is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h of each chips.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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power-domains:
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maxItems: 1
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clocks:
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minItems: 1
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iommus:
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maxItems: 1
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required:
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- compatible
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- reg
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- mediatek,gce-client-reg
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- mediatek,gce-events
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- power-domains
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- clocks
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- iommus
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/gce/mt8183-gce.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/memory/mt8183-larb-port.h>
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mdp3_wrot0: mdp3-wrot0@14005000 {
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compatible = "mediatek,mt8183-mdp3-wrot";
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reg = <0x14005000 0x1000>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
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mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
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<CMDQ_EVENT_MDP_WROT0_EOF>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_MDP_WROT0>;
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iommus = <&iommu>;
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};

‎Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml‎

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- mediatek,mt8173-vcodec-enc-vp8
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- mediatek,mt8173-vcodec-enc
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- mediatek,mt8183-vcodec-enc
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- mediatek,mt8188-vcodec-enc
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- mediatek,mt8192-vcodec-enc
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- mediatek,mt8195-vcodec-enc
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‎Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml‎

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enum:
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- mediatek,mt8192-vcodec-dec
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- mediatek,mt8186-vcodec-dec
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- mediatek,mt8188-vcodec-dec
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- mediatek,mt8195-vcodec-dec
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reg:

‎Documentation/devicetree/bindings/media/nxp,dw100.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/nxp,dw100.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8MP DW100 Dewarper core
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maintainers:
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- Xavier Roumegue <[email protected]>
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description: |-
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The Dewarp Engine provides high-performance dewarp processing for the
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correction of the distortion that is introduced in images produced by fisheye
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and wide angle lenses. It is implemented with a line/tile-cache based
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architecture. With configurable address mapping look up tables and per tile
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processing, it successfully generates a corrected output image.
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The engine can be used to perform scaling, cropping and pixel format
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conversion.
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properties:
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compatible:
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enum:
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- nxp,imx8mp-dw100
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: The AXI clock
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- description: The AHB clock
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clock-names:
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items:
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- const: axi
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- const: ahb
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/imx8mp-power.h>
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dewarp: dwe@32e30000 {
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compatible = "nxp,imx8mp-dw100";
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reg = <0x32e30000 0x10000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
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clock-names = "axi", "ahb";
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power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
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};

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