serial: sifive: enable clocks for UART when probed

When the PWM driver was changed to disable clocks if no PWMs are enabled,
it ended up also disabling the shared parent with the UART, since the
UART doesn't do any clock enablement on its own.

To avoid these surprises, switch to clk_get_enabled().

Fixes: ace41d7 ("pwm: sifive: Ensure the clk is enabled exactly once per running PWM")
Cc: stable <[email protected]>
Cc: Uwe Kleine-König <[email protected]>
Cc: Emil Renner Berthing <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Paul Walmsley <[email protected]>
Reviewed-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Uwe Kleine-König <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

Author: olofj

drivers/tty/serial/sifive.c

@@ -945,7 +945,7 @@ static int sifive_serial_probe(struct platform_device *pdev)
 		return PTR_ERR(base);
 	}
 
-	clk = devm_clk_get(&pdev->dev, NULL);
+	clk = devm_clk_get_enabled(&pdev->dev, NULL);
 	if (IS_ERR(clk)) {
 		dev_err(&pdev->dev, "unable to find controller clock\n");
 		return PTR_ERR(clk);