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airliedairlied
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Merge tag 'amd-drm-next-6.2-2022-12-07' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.2-2022-12-07: amdgpu: - DSC fixes for DCN 2.1 - HDMI PCON fixes - PSR fixes - DC DML fixes - Properly throttle on BO allocation - GFX 11.0.4 fixes - MMHUB fix - Make some functions static Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 9e5737b + 347fafe commit 66efff5

37 files changed

+156
-94
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c‎

Lines changed: 3 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
113113
bp.resv = resv;
114114
bp.preferred_domain = initial_domain;
115115
bp.flags = flags;
116-
bp.domain = initial_domain;
116+
bp.domain = initial_domain | AMDGPU_GEM_DOMAIN_CPU;
117117
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
118118

119119
r = amdgpu_bo_create_user(adev, &bp, &ubo);
@@ -332,20 +332,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
332332
}
333333

334334
initial_domain = (u32)(0xffffffff & args->in.domains);
335-
retry:
336335
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
337-
initial_domain,
338-
flags, ttm_bo_type_device, resv, &gobj);
336+
initial_domain, flags, ttm_bo_type_device,
337+
resv, &gobj);
339338
if (r && r != -ERESTARTSYS) {
340-
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
341-
flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
342-
goto retry;
343-
}
344-
345-
if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
346-
initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
347-
goto retry;
348-
}
349339
DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
350340
size, initial_domain, args->in.alignment, r);
351341
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -549,6 +549,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
549549
/* YELLOW_CARP*/
550550
case IP_VERSION(10, 3, 3):
551551
case IP_VERSION(11, 0, 1):
552+
case IP_VERSION(11, 0, 4):
552553
/* Don't enable it by default yet.
553554
*/
554555
if (amdgpu_tmz < 1) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.c‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -581,11 +581,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
581581
bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
582582

583583
bo->tbo.bdev = &adev->mman.bdev;
584-
if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
585-
AMDGPU_GEM_DOMAIN_GDS))
586-
amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
587-
else
588-
amdgpu_bo_placement_from_domain(bo, bp->domain);
584+
amdgpu_bo_placement_from_domain(bo, bp->domain);
589585
if (bp->type == ttm_bo_type_kernel)
590586
bo->tbo.priority = 1;
591587

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -350,7 +350,7 @@ unsigned int amdgpu_sw_ring_priority(int idx)
350350
}
351351

352352
/*Scan on low prio rings to have unsignaled fence and high ring has no fence.*/
353-
int amdgpu_mcbp_scan(struct amdgpu_ring_mux *mux)
353+
static int amdgpu_mcbp_scan(struct amdgpu_ring_mux *mux)
354354
{
355355
struct amdgpu_ring *ring;
356356
int i, need_preempt;
@@ -370,7 +370,7 @@ int amdgpu_mcbp_scan(struct amdgpu_ring_mux *mux)
370370
}
371371

372372
/* Trigger Mid-Command Buffer Preemption (MCBP) and find if we need to resubmit. */
373-
int amdgpu_mcbp_trigger_preempt(struct amdgpu_ring_mux *mux)
373+
static int amdgpu_mcbp_trigger_preempt(struct amdgpu_ring_mux *mux)
374374
{
375375
int r;
376376

@@ -434,7 +434,7 @@ void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *r
434434

435435
static void scan_and_remove_signaled_chunk(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring)
436436
{
437-
uint32_t last_seq, size = 0;
437+
uint32_t last_seq = 0;
438438
struct amdgpu_mux_entry *e;
439439
struct amdgpu_mux_chunk *chunk, *tmp;
440440

@@ -450,8 +450,6 @@ static void scan_and_remove_signaled_chunk(struct amdgpu_ring_mux *mux, struct a
450450
if (chunk->sync_seq <= last_seq) {
451451
list_del(&chunk->entry);
452452
kmem_cache_free(amdgpu_mux_chunk_slab, chunk);
453-
} else {
454-
size++;
455453
}
456454
}
457455
}

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5058,6 +5058,7 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
50585058
if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
50595059
switch (adev->ip_versions[GC_HWIP][0]) {
50605060
case IP_VERSION(11, 0, 1):
5061+
case IP_VERSION(11, 0, 4):
50615062
WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
50625063
break;
50635064
default:
@@ -5091,6 +5092,7 @@ static int gfx_v11_0_set_powergating_state(void *handle,
50915092
amdgpu_gfx_off_ctrl(adev, enable);
50925093
break;
50935094
case IP_VERSION(11, 0, 1):
5095+
case IP_VERSION(11, 0, 4):
50945096
gfx_v11_cntl_pg(adev, enable);
50955097
amdgpu_gfx_off_ctrl(adev, enable);
50965098
break;
@@ -5114,6 +5116,7 @@ static int gfx_v11_0_set_clockgating_state(void *handle,
51145116
case IP_VERSION(11, 0, 1):
51155117
case IP_VERSION(11, 0, 2):
51165118
case IP_VERSION(11, 0, 3):
5119+
case IP_VERSION(11, 0, 4):
51175120
gfx_v11_0_update_gfx_clock_gating(adev,
51185121
state == AMD_CG_STATE_GATE);
51195122
break;

‎drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
319319

320320
tmp = mmMMVM_L2_CNTL5_DEFAULT;
321321
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
322-
WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
322+
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
323323
}
324324

325325
static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -243,7 +243,7 @@ static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)
243243

244244
tmp = mmMMVM_L2_CNTL5_DEFAULT;
245245
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
246-
WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
246+
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
247247
}
248248

249249
static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -275,7 +275,7 @@ static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev)
275275

276276
tmp = regMMVM_L2_CNTL5_DEFAULT;
277277
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
278-
WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
278+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
279279
}
280280

281281
static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -269,7 +269,7 @@ static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
269269

270270
tmp = regMMVM_L2_CNTL5_DEFAULT;
271271
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
272-
WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
272+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
273273
}
274274

275275
static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev)
268268

269269
tmp = regMMVM_L2_CNTL5_DEFAULT;
270270
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
271-
WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
271+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
272272
}
273273

274274
static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev)

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