2121#include <asm/csr.h>
2222#include <asm/cacheflush.h>
2323#include <asm/hwcap.h>
24+ #include <asm/sbi.h>
2425
2526const struct _kvm_stats_desc kvm_vcpu_stats_desc [] = {
2627 KVM_GENERIC_VCPU_STATS (),
@@ -171,6 +172,11 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
171172 set_bit (host_isa , vcpu -> arch .isa );
172173 }
173174
175+ /* Setup vendor, arch, and implementation details */
176+ vcpu -> arch .mvendorid = sbi_get_mvendorid ();
177+ vcpu -> arch .marchid = sbi_get_marchid ();
178+ vcpu -> arch .mimpid = sbi_get_mimpid ();
179+
174180 /* Setup VCPU hfence queue */
175181 spin_lock_init (& vcpu -> arch .hfence_lock );
176182
@@ -270,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
270276 return - EINVAL ;
271277 reg_val = riscv_cbom_block_size ;
272278 break ;
279+ case KVM_REG_RISCV_CONFIG_REG (mvendorid ):
280+ reg_val = vcpu -> arch .mvendorid ;
281+ break ;
282+ case KVM_REG_RISCV_CONFIG_REG (marchid ):
283+ reg_val = vcpu -> arch .marchid ;
284+ break ;
285+ case KVM_REG_RISCV_CONFIG_REG (mimpid ):
286+ reg_val = vcpu -> arch .mimpid ;
287+ break ;
273288 default :
274289 return - EINVAL ;
275290 }
@@ -296,12 +311,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
296311 if (copy_from_user (& reg_val , uaddr , KVM_REG_SIZE (reg -> id )))
297312 return - EFAULT ;
298313
299- /* This ONE REG interface is only defined for single letter extensions */
300- if (fls (reg_val ) >= RISCV_ISA_EXT_BASE )
301- return - EINVAL ;
302-
303314 switch (reg_num ) {
304315 case KVM_REG_RISCV_CONFIG_REG (isa ):
316+ /*
317+ * This ONE REG interface is only defined for
318+ * single letter extensions.
319+ */
320+ if (fls (reg_val ) >= RISCV_ISA_EXT_BASE )
321+ return - EINVAL ;
322+
305323 if (!vcpu -> arch .ran_atleast_once ) {
306324 /* Ignore the enable/disable request for certain extensions */
307325 for (i = 0 ; i < RISCV_ISA_EXT_BASE ; i ++ ) {
@@ -329,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
329347 break ;
330348 case KVM_REG_RISCV_CONFIG_REG (zicbom_block_size ):
331349 return - EOPNOTSUPP ;
350+ case KVM_REG_RISCV_CONFIG_REG (mvendorid ):
351+ if (!vcpu -> arch .ran_atleast_once )
352+ vcpu -> arch .mvendorid = reg_val ;
353+ else
354+ return - EBUSY ;
355+ break ;
356+ case KVM_REG_RISCV_CONFIG_REG (marchid ):
357+ if (!vcpu -> arch .ran_atleast_once )
358+ vcpu -> arch .marchid = reg_val ;
359+ else
360+ return - EBUSY ;
361+ break ;
362+ case KVM_REG_RISCV_CONFIG_REG (mimpid ):
363+ if (!vcpu -> arch .ran_atleast_once )
364+ vcpu -> arch .mimpid = reg_val ;
365+ else
366+ return - EBUSY ;
367+ break ;
332368 default :
333369 return - EINVAL ;
334370 }
@@ -541,45 +577,53 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
541577static int kvm_riscv_vcpu_set_reg (struct kvm_vcpu * vcpu ,
542578 const struct kvm_one_reg * reg )
543579{
544- if ((reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CONFIG )
580+ switch (reg -> id & KVM_REG_RISCV_TYPE_MASK ) {
581+ case KVM_REG_RISCV_CONFIG :
545582 return kvm_riscv_vcpu_set_reg_config (vcpu , reg );
546- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CORE )
583+ case KVM_REG_RISCV_CORE :
547584 return kvm_riscv_vcpu_set_reg_core (vcpu , reg );
548- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CSR )
585+ case KVM_REG_RISCV_CSR :
549586 return kvm_riscv_vcpu_set_reg_csr (vcpu , reg );
550- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_TIMER )
587+ case KVM_REG_RISCV_TIMER :
551588 return kvm_riscv_vcpu_set_reg_timer (vcpu , reg );
552- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_F )
589+ case KVM_REG_RISCV_FP_F :
553590 return kvm_riscv_vcpu_set_reg_fp (vcpu , reg ,
554591 KVM_REG_RISCV_FP_F );
555- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_D )
592+ case KVM_REG_RISCV_FP_D :
556593 return kvm_riscv_vcpu_set_reg_fp (vcpu , reg ,
557594 KVM_REG_RISCV_FP_D );
558- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_ISA_EXT )
595+ case KVM_REG_RISCV_ISA_EXT :
559596 return kvm_riscv_vcpu_set_reg_isa_ext (vcpu , reg );
597+ default :
598+ break ;
599+ }
560600
561601 return - EINVAL ;
562602}
563603
564604static int kvm_riscv_vcpu_get_reg (struct kvm_vcpu * vcpu ,
565605 const struct kvm_one_reg * reg )
566606{
567- if ((reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CONFIG )
607+ switch (reg -> id & KVM_REG_RISCV_TYPE_MASK ) {
608+ case KVM_REG_RISCV_CONFIG :
568609 return kvm_riscv_vcpu_get_reg_config (vcpu , reg );
569- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CORE )
610+ case KVM_REG_RISCV_CORE :
570611 return kvm_riscv_vcpu_get_reg_core (vcpu , reg );
571- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CSR )
612+ case KVM_REG_RISCV_CSR :
572613 return kvm_riscv_vcpu_get_reg_csr (vcpu , reg );
573- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_TIMER )
614+ case KVM_REG_RISCV_TIMER :
574615 return kvm_riscv_vcpu_get_reg_timer (vcpu , reg );
575- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_F )
616+ case KVM_REG_RISCV_FP_F :
576617 return kvm_riscv_vcpu_get_reg_fp (vcpu , reg ,
577618 KVM_REG_RISCV_FP_F );
578- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_D )
619+ case KVM_REG_RISCV_FP_D :
579620 return kvm_riscv_vcpu_get_reg_fp (vcpu , reg ,
580621 KVM_REG_RISCV_FP_D );
581- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_ISA_EXT )
622+ case KVM_REG_RISCV_ISA_EXT :
582623 return kvm_riscv_vcpu_get_reg_isa_ext (vcpu , reg );
624+ default :
625+ break ;
626+ }
583627
584628 return - EINVAL ;
585629}
@@ -984,8 +1028,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9841028 while (ret > 0 ) {
9851029 /* Check conditions before entering the guest */
9861030 ret = xfer_to_guest_mode_handle_work (vcpu );
987- if (!ret )
988- ret = 1 ;
1031+ if (ret )
1032+ continue ;
1033+ ret = 1 ;
9891034
9901035 kvm_riscv_gstage_vmid_update (vcpu );
9911036
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