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robclarkrobclark
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drm/msm/adreno: Simplify read64/write64 helpers
The _HI reg is always following the _LO reg, so no need to pass these offsets seprately. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/511581/ Link: https://lore.kernel.org/r/[email protected]
1 parent e8b8feb commit cade05b

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6 files changed

+27
-46
lines changed

6 files changed

+27
-46
lines changed

‎drivers/gpu/drm/msm/adreno/a4xx_gpu.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -606,8 +606,7 @@ static int a4xx_pm_suspend(struct msm_gpu *gpu) {
606606

607607
static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
608608
{
609-
*value = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO,
610-
REG_A4XX_RBBM_PERFCTR_CP_0_HI);
609+
*value = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO);
611610

612611
return 0;
613612
}

‎drivers/gpu/drm/msm/adreno/a5xx_gpu.c‎

Lines changed: 10 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -605,11 +605,9 @@ static int a5xx_ucode_init(struct msm_gpu *gpu)
605605
a5xx_ucode_check_version(a5xx_gpu, a5xx_gpu->pfp_bo);
606606
}
607607

608-
gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO,
609-
REG_A5XX_CP_ME_INSTR_BASE_HI, a5xx_gpu->pm4_iova);
608+
gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO, a5xx_gpu->pm4_iova);
610609

611-
gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO,
612-
REG_A5XX_CP_PFP_INSTR_BASE_HI, a5xx_gpu->pfp_iova);
610+
gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO, a5xx_gpu->pfp_iova);
613611

614612
return 0;
615613
}
@@ -868,8 +866,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
868866
* memory rendering at this point in time and we don't want to block off
869867
* part of the virtual memory space.
870868
*/
871-
gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
872-
REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
869+
gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 0x00000000);
873870
gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
874871

875872
/* Put the GPU into 64 bit by default */
@@ -908,8 +905,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
908905
return ret;
909906

910907
/* Set the ringbuffer address */
911-
gpu_write64(gpu, REG_A5XX_CP_RB_BASE, REG_A5XX_CP_RB_BASE_HI,
912-
gpu->rb[0]->iova);
908+
gpu_write64(gpu, REG_A5XX_CP_RB_BASE, gpu->rb[0]->iova);
913909

914910
/*
915911
* If the microcode supports the WHERE_AM_I opcode then we can use that
@@ -936,7 +932,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
936932
}
937933

938934
gpu_write64(gpu, REG_A5XX_CP_RB_RPTR_ADDR,
939-
REG_A5XX_CP_RB_RPTR_ADDR_HI, shadowptr(a5xx_gpu, gpu->rb[0]));
935+
shadowptr(a5xx_gpu, gpu->rb[0]));
940936
} else if (gpu->nr_rings > 1) {
941937
/* Disable preemption if WHERE_AM_I isn't available */
942938
a5xx_preempt_fini(gpu);
@@ -1239,9 +1235,9 @@ static void a5xx_fault_detect_irq(struct msm_gpu *gpu)
12391235
gpu_read(gpu, REG_A5XX_RBBM_STATUS),
12401236
gpu_read(gpu, REG_A5XX_CP_RB_RPTR),
12411237
gpu_read(gpu, REG_A5XX_CP_RB_WPTR),
1242-
gpu_read64(gpu, REG_A5XX_CP_IB1_BASE, REG_A5XX_CP_IB1_BASE_HI),
1238+
gpu_read64(gpu, REG_A5XX_CP_IB1_BASE),
12431239
gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ),
1244-
gpu_read64(gpu, REG_A5XX_CP_IB2_BASE, REG_A5XX_CP_IB2_BASE_HI),
1240+
gpu_read64(gpu, REG_A5XX_CP_IB2_BASE),
12451241
gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ));
12461242

12471243
/* Turn off the hangcheck timer to keep it from bothering us */
@@ -1427,8 +1423,7 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
14271423

14281424
static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
14291425
{
1430-
*value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO,
1431-
REG_A5XX_RBBM_ALWAYSON_COUNTER_HI);
1426+
*value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO);
14321427

14331428
return 0;
14341429
}
@@ -1465,8 +1460,7 @@ static int a5xx_crashdumper_run(struct msm_gpu *gpu,
14651460
if (IS_ERR_OR_NULL(dumper->ptr))
14661461
return -EINVAL;
14671462

1468-
gpu_write64(gpu, REG_A5XX_CP_CRASH_SCRIPT_BASE_LO,
1469-
REG_A5XX_CP_CRASH_SCRIPT_BASE_HI, dumper->iova);
1463+
gpu_write64(gpu, REG_A5XX_CP_CRASH_SCRIPT_BASE_LO, dumper->iova);
14701464

14711465
gpu_write(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, 1);
14721466

@@ -1666,8 +1660,7 @@ static u64 a5xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
16661660
{
16671661
u64 busy_cycles;
16681662

1669-
busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,
1670-
REG_A5XX_RBBM_PERFCTR_RBBM_0_HI);
1663+
busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO);
16711664
*out_sample_rate = clk_get_rate(gpu->core_clk);
16721665

16731666
return busy_cycles;

‎drivers/gpu/drm/msm/adreno/a5xx_preempt.c‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,6 @@ void a5xx_preempt_trigger(struct msm_gpu *gpu)
137137

138138
/* Set the address of the incoming preemption record */
139139
gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO,
140-
REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI,
141140
a5xx_gpu->preempt_iova[ring->id]);
142141

143142
a5xx_gpu->next_ring = ring;
@@ -211,8 +210,7 @@ void a5xx_preempt_hw_init(struct msm_gpu *gpu)
211210
}
212211

213212
/* Write a 0 to signal that we aren't switching pagetables */
214-
gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO,
215-
REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI, 0);
213+
gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO, 0);
216214

217215
/* Reset the preemption state */
218216
set_preempt_state(a5xx_gpu, PREEMPT_NONE);

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -247,8 +247,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
247247
OUT_RING(ring, submit->seqno);
248248

249249
trace_msm_gpu_submit_flush(submit,
250-
gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
251-
REG_A6XX_CP_ALWAYS_ON_COUNTER_HI));
250+
gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO));
252251

253252
a6xx_flush(gpu, ring);
254253
}
@@ -947,8 +946,7 @@ static int a6xx_ucode_init(struct msm_gpu *gpu)
947946
}
948947
}
949948

950-
gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE,
951-
REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova);
949+
gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova);
952950

953951
return 0;
954952
}
@@ -999,8 +997,7 @@ static int hw_init(struct msm_gpu *gpu)
999997
* memory rendering at this point in time and we don't want to block off
1000998
* part of the virtual memory space.
1001999
*/
1002-
gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
1003-
REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
1000+
gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 0x00000000);
10041001
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
10051002

10061003
/* Turn on 64 bit addressing for all blocks */
@@ -1049,11 +1046,9 @@ static int hw_init(struct msm_gpu *gpu)
10491046

10501047
if (!adreno_is_a650_family(adreno_gpu)) {
10511048
/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
1052-
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
1053-
REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
1049+
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000);
10541050

10551051
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
1056-
REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
10571052
0x00100000 + adreno_gpu->gmem - 1);
10581053
}
10591054

@@ -1145,8 +1140,7 @@ static int hw_init(struct msm_gpu *gpu)
11451140
goto out;
11461141

11471142
/* Set the ringbuffer address */
1148-
gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
1149-
gpu->rb[0]->iova);
1143+
gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova);
11501144

11511145
/* Targets that support extended APRIV can use the RPTR shadow from
11521146
* hardware but all the other ones need to disable the feature. Targets
@@ -1178,7 +1172,6 @@ static int hw_init(struct msm_gpu *gpu)
11781172
}
11791173

11801174
gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO,
1181-
REG_A6XX_CP_RB_RPTR_ADDR_HI,
11821175
shadowptr(a6xx_gpu, gpu->rb[0]));
11831176
}
11841177

@@ -1499,9 +1492,9 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
14991492
gpu_read(gpu, REG_A6XX_RBBM_STATUS),
15001493
gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
15011494
gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1502-
gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
1495+
gpu_read64(gpu, REG_A6XX_CP_IB1_BASE),
15031496
gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
1504-
gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
1497+
gpu_read64(gpu, REG_A6XX_CP_IB2_BASE),
15051498
gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
15061499

15071500
/* Turn off the hangcheck timer to keep it from bothering us */
@@ -1712,8 +1705,7 @@ static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
17121705
/* Force the GPU power on so we can read this register */
17131706
a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
17141707

1715-
*value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
1716-
REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);
1708+
*value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO);
17171709

17181710
a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
17191711

‎drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -147,8 +147,7 @@ static int a6xx_crashdumper_run(struct msm_gpu *gpu,
147147
/* Make sure all pending memory writes are posted */
148148
wmb();
149149

150-
gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE_LO,
151-
REG_A6XX_CP_CRASH_SCRIPT_BASE_HI, dumper->iova);
150+
gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE_LO, dumper->iova);
152151

153152
gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1);
154153

‎drivers/gpu/drm/msm/msm_gpu.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -536,7 +536,7 @@ static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
536536
msm_rmw(gpu->mmio + (reg << 2), mask, or);
537537
}
538538

539-
static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
539+
static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)
540540
{
541541
u64 val;
542542

@@ -554,17 +554,17 @@ static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
554554
* when the lo is read, so make sure to read the lo first to trigger
555555
* that
556556
*/
557-
val = (u64) msm_readl(gpu->mmio + (lo << 2));
558-
val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
557+
val = (u64) msm_readl(gpu->mmio + (reg << 2));
558+
val |= ((u64) msm_readl(gpu->mmio + ((reg + 1) << 2)) << 32);
559559

560560
return val;
561561
}
562562

563-
static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
563+
static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)
564564
{
565565
/* Why not a writeq here? Read the screed above */
566-
msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
567-
msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
566+
msm_writel(lower_32_bits(val), gpu->mmio + (reg << 2));
567+
msm_writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
568568
}
569569

570570
int msm_gpu_pm_suspend(struct msm_gpu *gpu);

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