Merge tag 'gpio-updates-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

Pull gpio updates from Bartosz Golaszewski:
 "We have a single new driver, new features in others and some cleanups
  all over the place.

  Nothing really stands out and it is all relatively small.

   - new driver: gpio-modepin (plus relevant change in zynqmp firmware)

   - add interrupt support to gpio-virtio

   - enable the 'gpio-line-names' property in the DT bindings for
     gpio-rockchip

   - use the subsystem helpers where applicable in gpio-uniphier instead
     of accessing IRQ structures directly

   - code shrink in gpio-xilinx

   - add interrupt to gpio-mlxbf2 (and include the removal of custom
     interrupt code from the mellanox ethernet driver)

   - support multiple interrupts per bank in gpio-tegra186 (and force
     one interrupt per bank in older models)

   - fix GPIO line IRQ offset calculation in gpio-realtek-otto

   - drop unneeded MODULE_ALIAS expansions in multiple drivers

   - code cleanup in gpio-aggregator

   - minor improvements in gpio-max730x and gpio-mc33880

   - Kconfig cleanups"

* tag 'gpio-updates-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux:
  virtio_gpio: drop packed attribute
  gpio: virtio: Add IRQ support
  gpio: realtek-otto: fix GPIO line IRQ offset
  gpio: clean up Kconfig file
  net: mellanox: mlxbf_gige: Replace non-standard interrupt handling
  gpio: mlxbf2: Introduce IRQ support
  gpio: mc33880: Drop if with an always false condition
  gpio: max730x: Make __max730x_remove() return void
  gpio: aggregator: Wrap access to gpiochip_fwd.tmp[]
  gpio: modepin: Add driver support for modepin GPIO controller
  dt-bindings: gpio: zynqmp: Add binding documentation for modepin
  firmware: zynqmp: Add MMIO read and write support for PS_MODE pin
  gpio: tps65218: drop unneeded MODULE_ALIAS
  gpio: max77620: drop unneeded MODULE_ALIAS
  gpio: xilinx: simplify getting .driver_data
  gpio: tegra186: Support multiple interrupts per bank
  gpio: tegra186: Force one interrupt per bank
  gpio: uniphier: Use helper functions to get private data from IRQ data
  gpio: uniphier: Use helper function to get IRQ hardware number
  dt-bindings: gpio: add gpio-line-names to rockchip,gpio-bank.yaml

Author: torvalds

Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml

@@ -29,6 +29,8 @@ properties:
 
   gpio-controller: true
 
+  gpio-line-names: true
+
   "#gpio-cells":
     const: 2
 

Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: ZynqMP Mode Pin GPIO controller
+
+description:
+  PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
+  GPIO controller with configurable from numbers of pins (from 0 to 3 per
+  PS_MODE). Every pin can be configured as input/output.
+
+maintainers:
+  - Piyush Mehta <[email protected]>
+
+properties:
+  compatible:
+    const: xlnx,zynqmp-gpio-modepin
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+
+required:
+  - compatible
+  - gpio-controller
+  - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    zynqmp-firmware {
+        gpio {
+            compatible = "xlnx,zynqmp-gpio-modepin";
+            gpio-controller;
+            #gpio-cells = <2>;
+        };
+    };
+
+...

drivers/firmware/xilinx/zynqmp.c

@@ -28,6 +28,13 @@
 /* Max HashMap Order for PM API feature check (1<<7 = 128) */
 #define PM_API_FEATURE_CHECK_MAX_ORDER  7
 
+/* CRL registers and bitfields */
+#define CRL_APB_BASE			0xFF5E0000U
+/* BOOT_PIN_CTRL- Used to control the mode pins after boot */
+#define CRL_APB_BOOT_PIN_CTRL		(CRL_APB_BASE + (0x250U))
+/* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
+#define CRL_APB_BOOTPIN_CTRL_MASK	0xF0FU
+
 static bool feature_check_enabled;
 static DEFINE_HASHTABLE(pm_api_features_map, PM_API_FEATURE_CHECK_MAX_ORDER);
 
@@ -942,6 +949,45 @@ int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_config);
 
+/**
+ * zynqmp_pm_bootmode_read() - PM Config API for read bootpin status
+ * @ps_mode: Returned output value of ps_mode
+ *
+ * This API function is to be used for notify the power management controller
+ * to read bootpin status.
+ *
+ * Return: status, either success or error+reason
+ */
+unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
+{
+	unsigned int ret;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+
+	ret = zynqmp_pm_invoke_fn(PM_MMIO_READ, CRL_APB_BOOT_PIN_CTRL, 0,
+				  0, 0, ret_payload);
+
+	*ps_mode = ret_payload[1];
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_read);
+
+/**
+ * zynqmp_pm_bootmode_write() - PM Config API for Configure bootpin
+ * @ps_mode: Value to be written to the bootpin ctrl register
+ *
+ * This API function is to be used for notify the power management controller
+ * to configure bootpin.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_bootmode_write(u32 ps_mode)
+{
+	return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, CRL_APB_BOOT_PIN_CTRL,
+				   CRL_APB_BOOTPIN_CTRL_MASK, ps_mode, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_write);
+
 /**
  * zynqmp_pm_init_finalize() - PM call to inform firmware that the caller
  *			       master has initialized its own power management