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airliedairlied
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Merge tag 'drm-msm-fixes-2023-01-12' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
msm-fixes for v6.3-rc4 Display Fixes: - Fix the documentation for dpu_encoder_phys_wb_init() and dpu_encoder_phys_wb_setup_fb() APIs to address doc warnings - Remove vcca-supply and vdds-supply as mandatory for 14nm PHY and 10nm PHY DT schemas respectively as they are not present on some SOCs using these PHYs - Add the dsi-phy-regulator-ldo-mode to dsi-phy-28nm.yaml as it was missed out during txt to yaml migration - Remove operating-points-v2 and power-domain as a required property for the DSI controller as thats not the case for every SOC - Fix the description from display escape clock to display core clock in the dsi controller yaml - Fix the memory leak for mdp1-mem path for the cases when we return early after failing to get mdp0-mem ICC paths for msm - Fix error handling path in msm_hdmi_dev_probe() to release the phy ref count when devm_pm_runtime_enable() fails - Fix the dp_aux_isr() routine to make sure it doesnt incorrectly signal the aux transaction as complete if the ISR was not an AUX isr. This fixes a big hitter stability bug on chromebooks. - Add protection against null pointer dereference when there is no kms object as in the case of headless adreno GPU in the shutdown path. GPU Fixes: - a5xx: fix quirks to actually be a bitmask and not overwrite each other - a6xx: fix gx halt sequence to avoid 1000ms hang on some devices - kexec shutdown fix - fix potential double free Signed-off-by: Dave Airlie <[email protected]> From: Rob Clark <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGv7=in_MHW3kdkhqh7ZFoVCmnikmr29YYHCXR=7aOEneg@mail.gmail.com
2 parents 5188388 + f4a75b5 commit e695bc7

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‎Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ properties:
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- description: Display byte clock
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- description: Display byte interface clock
3434
- description: Display pixel clock
35-
- description: Display escape clock
35+
- description: Display core clock
3636
- description: Display AHB clock
3737
- description: Display AXI clock
3838

@@ -137,8 +137,6 @@ required:
137137
- phys
138138
- assigned-clocks
139139
- assigned-clock-parents
140-
- power-domains
141-
- operating-points-v2
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- ports
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additionalProperties: false

‎Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -69,7 +69,6 @@ required:
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- compatible
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- reg
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- reg-names
72-
- vdds-supply
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unevaluatedProperties: false
7574

‎Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml‎

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@@ -39,7 +39,6 @@ required:
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- compatible
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- reg
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- reg-names
42-
- vcca-supply
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unevaluatedProperties: false
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‎Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,10 @@ properties:
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vddio-supply:
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description: Phandle to vdd-io regulator device node.
3636

37+
qcom,dsi-phy-regulator-ldo-mode:
38+
type: boolean
39+
description: Indicates if the LDO mode PHY regulator is wanted.
40+
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ examples:
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#include <dt-bindings/interconnect/qcom,qcm2290.h>
7373
#include <dt-bindings/power/qcom-rpmpd.h>
7474
75-
mdss@5e00000 {
75+
display-subsystem@5e00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,qcm2290-mdss";

‎Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ examples:
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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65-
mdss@5e00000 {
65+
display-subsystem@5e00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,sm6115-mdss";

‎drivers/gpu/drm/msm/adreno/a6xx_gmu.c‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -876,7 +876,8 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
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#define GBIF_CLIENT_HALT_MASK BIT(0)
877877
#define GBIF_ARB_HALT_MASK BIT(1)
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879-
static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
879+
static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu,
880+
bool gx_off)
880881
{
881882
struct msm_gpu *gpu = &adreno_gpu->base;
882883

@@ -889,9 +890,11 @@ static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
889890
return;
890891
}
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892-
/* Halt the gx side of GBIF */
893-
gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1);
894-
spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1);
893+
if (gx_off) {
894+
/* Halt the gx side of GBIF */
895+
gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1);
896+
spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1);
897+
}
895898

896899
/* Halt new client requests on GBIF */
897900
gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
@@ -929,7 +932,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
929932
/* Halt the gmu cm3 core */
930933
gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
931934

932-
a6xx_bus_clear_pending_transactions(adreno_gpu);
935+
a6xx_bus_clear_pending_transactions(adreno_gpu, true);
933936

934937
/* Reset GPU core blocks */
935938
gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
@@ -1083,7 +1086,7 @@ static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
10831086
return;
10841087
}
10851088

1086-
a6xx_bus_clear_pending_transactions(adreno_gpu);
1089+
a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung);
10871090

10881091
/* tell the GMU we want to slumber */
10891092
ret = a6xx_gmu_notify_slumber(gmu);

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1270,6 +1270,12 @@ static void a6xx_recover(struct msm_gpu *gpu)
12701270
if (hang_debug)
12711271
a6xx_dump(gpu);
12721272

1273+
/*
1274+
* To handle recovery specific sequences during the rpm suspend we are
1275+
* about to trigger
1276+
*/
1277+
a6xx_gpu->hung = true;
1278+
12731279
/* Halt SQE first */
12741280
gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3);
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@@ -1312,6 +1318,7 @@ static void a6xx_recover(struct msm_gpu *gpu)
13121318
mutex_unlock(&gpu->active_lock);
13131319

13141320
msm_gpu_hw_init(gpu);
1321+
a6xx_gpu->hung = false;
13151322
}
13161323

13171324
static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ struct a6xx_gpu {
3232
void *llc_slice;
3333
void *htw_llc_slice;
3434
bool have_mmu500;
35+
bool hung;
3536
};
3637

3738
#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)

‎drivers/gpu/drm/msm/adreno/adreno_gpu.h‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,9 @@ enum {
2929
ADRENO_FW_MAX,
3030
};
3131

32-
enum adreno_quirks {
33-
ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
34-
ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
35-
ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
36-
};
32+
#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
33+
#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
34+
#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
3735

3836
struct adreno_rev {
3937
uint8_t core;
@@ -65,7 +63,7 @@ struct adreno_info {
6563
const char *name;
6664
const char *fw[ADRENO_FW_MAX];
6765
uint32_t gmem;
68-
enum adreno_quirks quirks;
66+
u64 quirks;
6967
struct msm_gpu *(*init)(struct drm_device *dev);
7068
const char *zapfw;
7169
u32 inactive_period;

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