@@ -544,45 +544,53 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
544544static int kvm_riscv_vcpu_set_reg (struct kvm_vcpu * vcpu ,
545545 const struct kvm_one_reg * reg )
546546{
547- if ((reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CONFIG )
547+ switch (reg -> id & KVM_REG_RISCV_TYPE_MASK ) {
548+ case KVM_REG_RISCV_CONFIG :
548549 return kvm_riscv_vcpu_set_reg_config (vcpu , reg );
549- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CORE )
550+ case KVM_REG_RISCV_CORE :
550551 return kvm_riscv_vcpu_set_reg_core (vcpu , reg );
551- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CSR )
552+ case KVM_REG_RISCV_CSR :
552553 return kvm_riscv_vcpu_set_reg_csr (vcpu , reg );
553- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_TIMER )
554+ case KVM_REG_RISCV_TIMER :
554555 return kvm_riscv_vcpu_set_reg_timer (vcpu , reg );
555- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_F )
556+ case KVM_REG_RISCV_FP_F :
556557 return kvm_riscv_vcpu_set_reg_fp (vcpu , reg ,
557558 KVM_REG_RISCV_FP_F );
558- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_D )
559+ case KVM_REG_RISCV_FP_D :
559560 return kvm_riscv_vcpu_set_reg_fp (vcpu , reg ,
560561 KVM_REG_RISCV_FP_D );
561- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_ISA_EXT )
562+ case KVM_REG_RISCV_ISA_EXT :
562563 return kvm_riscv_vcpu_set_reg_isa_ext (vcpu , reg );
564+ default :
565+ break ;
566+ }
563567
564568 return - EINVAL ;
565569}
566570
567571static int kvm_riscv_vcpu_get_reg (struct kvm_vcpu * vcpu ,
568572 const struct kvm_one_reg * reg )
569573{
570- if ((reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CONFIG )
574+ switch (reg -> id & KVM_REG_RISCV_TYPE_MASK ) {
575+ case KVM_REG_RISCV_CONFIG :
571576 return kvm_riscv_vcpu_get_reg_config (vcpu , reg );
572- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CORE )
577+ case KVM_REG_RISCV_CORE :
573578 return kvm_riscv_vcpu_get_reg_core (vcpu , reg );
574- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_CSR )
579+ case KVM_REG_RISCV_CSR :
575580 return kvm_riscv_vcpu_get_reg_csr (vcpu , reg );
576- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_TIMER )
581+ case KVM_REG_RISCV_TIMER :
577582 return kvm_riscv_vcpu_get_reg_timer (vcpu , reg );
578- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_F )
583+ case KVM_REG_RISCV_FP_F :
579584 return kvm_riscv_vcpu_get_reg_fp (vcpu , reg ,
580585 KVM_REG_RISCV_FP_F );
581- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_FP_D )
586+ case KVM_REG_RISCV_FP_D :
582587 return kvm_riscv_vcpu_get_reg_fp (vcpu , reg ,
583588 KVM_REG_RISCV_FP_D );
584- else if (( reg -> id & KVM_REG_RISCV_TYPE_MASK ) == KVM_REG_RISCV_ISA_EXT )
589+ case KVM_REG_RISCV_ISA_EXT :
585590 return kvm_riscv_vcpu_get_reg_isa_ext (vcpu , reg );
591+ default :
592+ break ;
593+ }
586594
587595 return - EINVAL ;
588596}
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