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airliedairlied
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Merge tag 'amd-drm-fixes-6.2-2023-02-01' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.2-2023-02-01: amdgpu: - GC11 fixes - DCN 3.1.4 fixes - NBIO 4.3 fix - DCN 3.2 fixes - Properly handle additional cases where DCN is not supported - SMU13 fixes Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 74d6c8e + 6fc547a commit f1a9e82

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‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -790,8 +790,8 @@ static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd,
790790
* zero here */
791791
WARN_ON(simd != 0);
792792

793-
/* type 2 wave data */
794-
dst[(*no_fields)++] = 2;
793+
/* type 3 wave data */
794+
dst[(*no_fields)++] = 3;
795795
dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
796796
dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
797797
dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);

‎drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -337,7 +337,13 @@ const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg = {
337337

338338
static void nbio_v4_3_init_registers(struct amdgpu_device *adev)
339339
{
340-
return;
340+
if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(4, 3, 0)) {
341+
uint32_t data;
342+
343+
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);
344+
data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
345+
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
346+
}
341347
}
342348

343349
static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/soc21.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -640,7 +640,8 @@ static int soc21_common_early_init(void *handle)
640640
AMD_CG_SUPPORT_GFX_CGCG |
641641
AMD_CG_SUPPORT_GFX_CGLS |
642642
AMD_CG_SUPPORT_REPEATER_FGCG |
643-
AMD_CG_SUPPORT_GFX_MGCG;
643+
AMD_CG_SUPPORT_GFX_MGCG |
644+
AMD_CG_SUPPORT_HDP_SD;
644645
adev->pg_flags = AMD_PG_SUPPORT_VCN |
645646
AMD_PG_SUPPORT_VCN_DPG |
646647
AMD_PG_SUPPORT_JPEG;

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4501,6 +4501,17 @@ DEVICE_ATTR_WO(s3_debug);
45014501
static int dm_early_init(void *handle)
45024502
{
45034503
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4504+
struct amdgpu_mode_info *mode_info = &adev->mode_info;
4505+
struct atom_context *ctx = mode_info->atom_context;
4506+
int index = GetIndexIntoMasterTable(DATA, Object_Header);
4507+
u16 data_offset;
4508+
4509+
/* if there is no object header, skip DM */
4510+
if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4511+
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4512+
dev_info(adev->dev, "No object header, skipping DM\n");
4513+
return -ENOENT;
4514+
}
45044515

45054516
switch (adev->asic_type) {
45064517
#if defined(CONFIG_DRM_AMD_DC_SI)

‎drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -874,8 +874,9 @@ static const struct dc_plane_cap plane_cap = {
874874
},
875875

876876
// 6:1 downscaling ratio: 1000/6 = 166.666
877+
// 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250
877878
.max_downscale_factor = {
878-
.argb8888 = 167,
879+
.argb8888 = 250,
879880
.nv12 = 167,
880881
.fp16 = 167
881882
},
@@ -1763,7 +1764,7 @@ static bool dcn314_resource_construct(
17631764
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
17641765
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
17651766
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1766-
dc->caps.max_downscale_ratio = 600;
1767+
dc->caps.max_downscale_ratio = 400;
17671768
dc->caps.i2c_speed_in_khz = 100;
17681769
dc->caps.i2c_speed_in_khz_hdcp = 100;
17691770
dc->caps.max_cursor_size = 256;

‎drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
9494
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
9595
.calc_vupdate_position = dcn10_calc_vupdate_position,
9696
.apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations,
97-
.does_plane_fit_in_mall = dcn30_does_plane_fit_in_mall,
97+
.does_plane_fit_in_mall = NULL,
9898
.set_backlight_level = dcn21_set_backlight_level,
9999
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
100100
.hardware_release = dcn30_hardware_release,

‎drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3183,7 +3183,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
31833183
} else {
31843184
v->MIN_DST_Y_NEXT_START[k] = v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k];
31853185
}
3186-
v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / (double)v->HTotal[k] / v->PixelClock[k], 1.0) / 4.0;
3186+
v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / ((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
31873187
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
31883188
<= (isInterlaceTiming ?
31893189
dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :

‎drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -532,6 +532,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
532532
if (dmub->hw_funcs.reset)
533533
dmub->hw_funcs.reset(dmub);
534534

535+
/* reset the cache of the last wptr as well now that hw is reset */
536+
dmub->inbox1_last_wptr = 0;
537+
535538
cw0.offset.quad_part = inst_fb->gpu_addr;
536539
cw0.region.base = DMUB_CW0_BASE;
537540
cw0.region.top = cw0.region.base + inst_fb->size - 1;
@@ -649,6 +652,15 @@ enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
649652
if (dmub->hw_funcs.reset)
650653
dmub->hw_funcs.reset(dmub);
651654

655+
/* mailboxes have been reset in hw, so reset the sw state as well */
656+
dmub->inbox1_last_wptr = 0;
657+
dmub->inbox1_rb.wrpt = 0;
658+
dmub->inbox1_rb.rptr = 0;
659+
dmub->outbox0_rb.wrpt = 0;
660+
dmub->outbox0_rb.rptr = 0;
661+
dmub->outbox1_rb.wrpt = 0;
662+
dmub->outbox1_rb.rptr = 0;
663+
652664
dmub->hw_init = false;
653665

654666
return DMUB_STATUS_OK;

‎drivers/gpu/drm/amd/pm/amdgpu_pm.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2007,14 +2007,16 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
20072007
gc_ver == IP_VERSION(10, 3, 0) ||
20082008
gc_ver == IP_VERSION(10, 1, 2) ||
20092009
gc_ver == IP_VERSION(11, 0, 0) ||
2010-
gc_ver == IP_VERSION(11, 0, 2)))
2010+
gc_ver == IP_VERSION(11, 0, 2) ||
2011+
gc_ver == IP_VERSION(11, 0, 3)))
20112012
*states = ATTR_STATE_UNSUPPORTED;
20122013
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
20132014
if (!(gc_ver == IP_VERSION(10, 3, 1) ||
20142015
gc_ver == IP_VERSION(10, 3, 0) ||
20152016
gc_ver == IP_VERSION(10, 1, 2) ||
20162017
gc_ver == IP_VERSION(11, 0, 0) ||
2017-
gc_ver == IP_VERSION(11, 0, 2)))
2018+
gc_ver == IP_VERSION(11, 0, 2) ||
2019+
gc_ver == IP_VERSION(11, 0, 3)))
20182020
*states = ATTR_STATE_UNSUPPORTED;
20192021
} else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
20202022
if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)

‎drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1499,6 +1499,20 @@ static int smu_disable_dpms(struct smu_context *smu)
14991499
}
15001500
}
15011501

1502+
/*
1503+
* For SMU 13.0.4/11, PMFW will handle the features disablement properly
1504+
* for gpu reset case. Driver involvement is unnecessary.
1505+
*/
1506+
if (amdgpu_in_reset(adev)) {
1507+
switch (adev->ip_versions[MP1_HWIP][0]) {
1508+
case IP_VERSION(13, 0, 4):
1509+
case IP_VERSION(13, 0, 11):
1510+
return 0;
1511+
default:
1512+
break;
1513+
}
1514+
}
1515+
15021516
/*
15031517
* For gpu reset, runpm and hibernation through BACO,
15041518
* BACO feature has to be kept enabled.

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