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Merge tag 'arm-late-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more ARM SoC updates from Arnd Bergmann: "These updates came in after I had already tagged the branches, but they still seem appropriate for 6.0 and most of them were part of linux-next through other trees. - The reset controller tree adds one new driver for the TI TPS380x power management chip and a few minor changes in other drivers - Apple M1 now has a DT entry for the NVMe controller after the driver was merged, and has a new mailing list in the MAINTAINERS file. - Fixes for USB on the Socionext Uniphier platforms and the network controller on Intel Cyclone5" * tag 'arm-late-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: uniphier: Fix USB interrupts for PXs3 SoC ARM: dts: uniphier: Fix USB interrupts for PXs2 SoC arm64: dts: apple: t8103: Add ANS2 NVMe nodes reset: tps380x: Fix spelling mistake "Voltags" -> "Voltage" reset: tps380x: Add TPS380x device driver supprt dt-bindings: reset: Add TPS380x documentation dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G2UL USBPHY Control bindings ARM: dts: add EMAC AXI settings for Cyclone5 reset: reset-simple should depends on HAS_IOMEM Revert "reset: microchip-sparx5: allow building as a module" reset: a10sr: allow building under COMPILE_TEST reset: allow building of reset simple driver if expert config selected reset: microchip-sparx5: allow building as a module arm64: dts: apple: Re-parent ANS2 power domains MAINTAINERS: add ARM/APPLE MACHINE mailing list
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‎Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml‎

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@@ -17,6 +17,7 @@ properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g043-usbphy-ctrl # RZ/G2UL
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- renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
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- renesas,r9a07g054-usbphy-ctrl # RZ/V2L
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- const: renesas,rzg2l-usbphy-ctrl

‎Documentation/devicetree/bindings/reset/ti,tps380x-reset.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/ti,tps380x-reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI TPS380x reset controller node bindings
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maintainers:
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- Marco Felsch <[email protected]>
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description: |
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The TPS380x family [1] of supervisory circuits monitor supply voltages to
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provide circuit initialization and timing supervision. The devices assert a
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RESET signal if the voltage drops below a preset threshold or upon a manual
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reset input (MR). The RESET output remains asserted for the factory
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programmed delay after the voltage return above its threshold or after the
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manual reset input is released.
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[1] https://www.ti.com/product/TPS3801
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properties:
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compatible:
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enum:
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- ti,tps3801
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reset-gpios:
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maxItems: 1
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description: Reference to the GPIO connected to the MR pin.
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"#reset-cells":
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const: 0
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required:
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- compatible
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- reset-gpios
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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reset: reset-controller {
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compatible = "ti,tps3801";
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#reset-cells = <0>;
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reset-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
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};
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...

‎MAINTAINERS‎

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@@ -1850,6 +1850,7 @@ ARM/APPLE MACHINE SUPPORT
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M: Hector Martin <[email protected]>
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M: Sven Peter <[email protected]>
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R: Alyssa Rosenzweig <[email protected]>
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L: [email protected]
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L: [email protected] (moderated for non-subscribers)
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S: Maintained
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W: https://asahilinux.org

‎arch/arm/boot/dts/socfpga.dtsi‎

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@@ -561,6 +561,12 @@
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interrupts = <0 175 4>;
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};
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socfpga_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <0xf>;
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snps,rd_osr_lmt = <0xf>;
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snps,blen = <0 0 0 0 16 0 0>;
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};
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gmac0: ethernet@ff700000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x60 0>;
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snps,perfect-filter-entries = <128>;
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tx-fifo-depth = <4096>;
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rx-fifo-depth = <4096>;
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snps,axi-config = <&socfpga_axi_setup>;
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status = "disabled";
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};
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snps,perfect-filter-entries = <128>;
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tx-fifo-depth = <4096>;
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rx-fifo-depth = <4096>;
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snps,axi-config = <&socfpga_axi_setup>;
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status = "disabled";
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};
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‎arch/arm/boot/dts/uniphier-pxs2.dtsi‎

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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65a00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 134 4>, <0 135 4>;
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interrupt-names = "dwc_usb3";
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interrupts = <0 134 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
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clock-names = "ref", "bus_early", "suspend";
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65c00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 137 4>, <0 138 4>;
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interrupt-names = "dwc_usb3";
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interrupts = <0 137 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
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clock-names = "ref", "bus_early", "suspend";

‎arch/arm64/boot/dts/apple/t8103-pmgr.dtsi‎

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#power-domain-cells = <0>;
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#reset-cells = <0>;
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label = "ans2";
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/*
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* The ADT makes ps_apcie_st depend on ps_ans2 instead, but this
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* doesn't make much sense since ANS2 uses APCIE_ST.
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*/
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power-domains = <&ps_apcie_st>;
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};
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ps_gfx: power-controller@3f8 {
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#power-domain-cells = <0>;
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#reset-cells = <0>;
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label = "apcie_st";
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power-domains = <&ps_apcie>;
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power-domains = <&ps_apcie>, <&ps_ans2>;
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};
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ps_ane_sys: power-controller@470 {

‎arch/arm64/boot/dts/apple/t8103.dtsi‎

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<AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
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};
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ans_mbox: mbox@277408000 {
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compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
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reg = <0x2 0x77408000 0x0 0x4000>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>,
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<AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "send-empty", "send-not-empty",
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"recv-empty", "recv-not-empty";
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#mbox-cells = <0>;
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power-domains = <&ps_ans2>;
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};
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sart: iommu@27bc50000 {
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compatible = "apple,t8103-sart";
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reg = <0x2 0x7bc50000 0x0 0x10000>;
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power-domains = <&ps_ans2>;
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};
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nvme@27bcc0000 {
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compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
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reg = <0x2 0x7bcc0000 0x0 0x40000>,
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<0x2 0x77400000 0x0 0x4000>;
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reg-names = "nvme", "ans";
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
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mboxes = <&ans_mbox>;
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apple,sart = <&sart>;
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power-domains = <&ps_ans2>, <&ps_apcie_st>;
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power-domain-names = "ans", "apcie0";
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resets = <&ps_ans2>;
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};
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pcie0_dart_0: dart@681008000 {
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compatible = "apple,t8103-dart";
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reg = <0x6 0x81008000 0x0 0x4000>;

‎arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi‎

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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65a00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 134 4>, <0 135 4>;
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interrupt-names = "dwc_usb3";
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interrupts = <0 134 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
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clock-names = "ref", "bus_early", "suspend";
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65c00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 137 4>, <0 138 4>;
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interrupt-names = "dwc_usb3";
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interrupts = <0 137 4>;
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pinctrl-names = "default";
707707
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
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clock-names = "ref", "bus_early", "suspend";

‎drivers/reset/Kconfig‎

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config RESET_A10SR
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tristate "Altera Arria10 System Resource Reset"
20-
depends on MFD_ALTERA_A10SR
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depends on MFD_ALTERA_A10SR || COMPILE_TEST
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help
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This option enables support for the external reset functions for
2323
peripheral PHYs on the Altera Arria10 System Resource Chip.
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200200
firmware controlling all the reset signals.
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202202
config RESET_SIMPLE
203-
bool "Simple Reset Controller Driver" if COMPILE_TEST
203+
bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
204204
default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
205+
depends on HAS_IOMEM
205206
help
206207
This enables a simple reset controller driver for reset lines that
207208
that can be asserted and deasserted by toggling bits in a contiguous,
@@ -265,6 +266,14 @@ config RESET_TI_SYSCON
265266
you wish to use the reset framework for such memory-mapped devices,
266267
say Y here. Otherwise, say N.
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269+
config RESET_TI_TPS380X
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tristate "TI TPS380x Reset Driver"
271+
select GPIOLIB
272+
help
273+
This enables the reset driver support for TI TPS380x devices. If
274+
you wish to use the reset framework for such devices, say Y here.
275+
Otherwise, say N.
276+
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config RESET_TN48M_CPLD
269278
tristate "Delta Networks TN48M switch CPLD reset controller"
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depends on MFD_TN48M_CPLD || COMPILE_TEST

‎drivers/reset/Makefile‎

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@@ -34,6 +34,7 @@ obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
3535
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
3636
obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
37+
obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o
3738
obj-$(CONFIG_RESET_TN48M_CPLD) += reset-tn48m.o
3839
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
3940
obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o

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