Add missing opcodes to 6502 core

[clydeshaffer]

The emulator's 6502 core was based on a project only emulating the original 6502

I've added:
WAI
TSB
TRB
BRA
PHX
PHY
PLX
PLY
STZ
STP

somebody should add the rest of them

This page talks about the extra opcodes
http://6502.org/tutorials/65c02opcodes.html

[clydeshaffer]

WDC datasheet https://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf

[nickgirardo]

I'm reading through the 6502.org page, I'm guessing that we also don't respect the changes to existing instructions? (e.g. ADC taking longer with the decimal flag set)

We should make a table of differences between 6502 and 65c02 and which have been implemented

[nickgirardo]

Instruction	Mode	Implemented	Change
ADC	(zp)	yes*	new addressing mode
AND	(zp)	yes	new addressing mode
CMP	(zp)	yes	new addressing mode
EOR	(zp)	yes	new addressing mode
LDA	(zp)	yes	new addressing mode
ORA	(zp)	yes	new addressing mode
SBC	(zp)	yes*	new addressing mode
STA	(zp)	yes	new addressing mode
BIT	imm	no	new addressing mode
BIT	zp, x	no	new addressing mode
BIT	abs, x	no	new addressing mode
DEC		yes	new opcode
INC		yes	new opcode
JMP	(abs, x)	no	new addressing mode
BRA		yes	new opcode
PHX		yes	new opcode
PHX		yes	new opcode
PLX		yes	new opcode
PLY		yes	new opcode
STZ		yes	new opcode
TRB		yes	new opcode
TSP		yes	new opcode
BBRx		no	new opcodes (x: 0-7)
BBSx		no	new opcodes (x: 0-7)
RMBx		no	new opcodes (x: 0-7)
SMBx		no	new opcodes (x: 0-7)
STP		yes	new opcode
WAI		yes	new opcode
BRK		no	D flag cleared
ASL LSR ROL ROR	abs, x	no	Only takes 6 cycles if page boundry not crossed
ADC		no	Different behavior if D set
SBC		no	Different behavior if D set
JMP	(abs)	no	Bugfix when operand low byte $FF

[clydeshaffer]

One thing I just realized is that the emulator core has no mechanism for defining that an opcode has a different cycle count under some conditions. So we'll need to come up with one