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.gitlab-ci.yml
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282 lines (249 loc) · 6.68 KB
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################################################################################
# Global definitions
#-------------------------------------------------------------------------------
variables:
VIVADO_VERSION: "2019.2"
HLS_COMMAND: "vivado_hls"
stages:
- Python checks
- Setup
- HLS checks
- Create projects
- Simulate
- Check simulation results
- Synthesize
- Implement
################################################################################
################################################################################
# Job templates
#-------------------------------------------------------------------------------
.vivado-job:
image: registry.cern.ch/ci4fpga/vivado:$VIVADO_VERSION
tags:
- fpga-mid
dependencies:
- download
after_script:
- cd emData/
- ./clean.sh > /dev/null 2>&1
artifacts:
name: "$CI_JOB_STAGE-$CI_JOB_NAME-$CI_COMMIT_REF_SLUG-$CI_COMMIT_SHORT_SHA"
untracked: true
expire_in: 1 week
.hls-job:
extends: .vivado-job
stage: HLS checks
variables:
NOUSE: Synthesis,Implementation
script:
- cd project/
- $HLS_COMMAND -f script_$MODULE.tcl
.create-project:
extends: .vivado-job
stage: Create projects
tags:
- fpga-large
variables:
NOUSE: Synthesis,Implementation
script:
- cd IntegrationTests/$PROJECT/script/
- make -j`nproc` Work
after_script:
- cd IntegrationTests/$PROJECT/script/
- rm -rf Work vivado*
- cd -
- cd emData/
- ./clean.sh > /dev/null 2>&1
.sim-project:
extends: .vivado-job
stage: Simulate
variables:
NOUSE: Synthesis,Implementation
script:
- cd IntegrationTests/$PROJECT/script/
- vivado -mode batch -source ./makeProject.tcl
- vivado -mode batch -source ./runSim.tcl
after_script:
- cd IntegrationTests/$PROJECT/script/
- find -mindepth 1 -maxdepth 1 -type d ! -regex ".*\/dataOut$" -exec rm -rf {} \;
- cd -
- cd emData/
- ./clean.sh > /dev/null 2>&1
.check-project:
stage: Check simulation results
image: registry.cern.ch/docker.io/library/python
before_script:
- pip install --root-user-action=ignore pandas
script:
- cd IntegrationTests/$PROJECT/script/
- python3 common/script/CompareMemPrintsFW.py -p -s
after_script:
- cd IntegrationTests/$PROJECT/script/
- find -mindepth 1 -maxdepth 1 -type l -exec rm -f {} \;
- rm -f vivado*
- cd -
- cd emData/
- ./clean.sh > /dev/null 2>&1
artifacts:
name: "$CI_JOB_STAGE-$CI_JOB_NAME-$CI_COMMIT_REF_SLUG-$CI_COMMIT_SHORT_SHA"
untracked: true
expire_in: 1 week
.synth-project:
extends: .vivado-job
stage: Synthesize
tags:
- fpga-large
variables:
NOUSE: Implementation
script:
- cd IntegrationTests/$PROJECT/script/
- vivado -mode batch -source ./makeProject.tcl
- vivado -mode batch -source ./common/script/synth.tcl
after_script:
- cd IntegrationTests/$PROJECT/script/
- find -mindepth 1 -maxdepth 1 -type d ! -regex ".*\/Work$" -exec rm -rf {} \;
- find -mindepth 1 -maxdepth 1 -type l -exec rm -f {} \;
- cd -
- cd emData/
- ./clean.sh > /dev/null 2>&1
.impl-project:
extends: .vivado-job
stage: Implement
tags:
- fpga-large
variables:
NOUSE: Synthesis
script:
- cd IntegrationTests/$PROJECT/script/
- vivado -mode batch -source ./common/script/impl.tcl
after_script:
- cd IntegrationTests/$PROJECT/script/
- find -mindepth 1 -maxdepth 1 -type d ! -regex ".*\/Work$" -exec rm -rf {} \;
- find -mindepth 1 -maxdepth 1 -type l -exec rm -f {} \;
- cd -
- cd emData/
- ./clean.sh > /dev/null 2>&1
################################################################################
################################################################################
# Job definitions
#-------------------------------------------------------------------------------
pylint:
stage: Python checks
image: registry.cern.ch/docker.io/library/python
before_script:
- pip install --root-user-action=ignore pylint
script:
- python3 -m pylint emData/*.py
download:
stage: Setup
image: registry.cern.ch/docker.io/library/python
script:
- cd emData/
- ./download.sh
artifacts:
name: "$CI_JOB_STAGE-$CI_JOB_NAME-$CI_COMMIT_REF_SLUG-$CI_COMMIT_SHORT_SHA"
untracked: true
expire_in: 1 week
### HLS checks
build-IR:
extends: .hls-job
variables:
MODULE: "IR"
build-MP:
extends: .hls-job
tags:
- fpga-large
variables:
MODULE: "MP"
build-PC:
extends: .hls-job
variables:
MODULE: "PC"
build-TB:
extends: .hls-job
variables:
MODULE: "TB"
build-TP:
extends: .hls-job
variables:
MODULE: "TP"
build-VMRCM:
extends: .hls-job
variables:
MODULE: "VMRCM"
build-VMSMER:
extends: .hls-job
variables:
MODULE: "VMSMER"
### Create projects
create-ReducedCombinedConfig_FPGA1:
extends: .create-project
variables:
PROJECT: "ReducedCombinedConfig_FPGA1"
create-ReducedCombinedConfig_FPGA2:
extends: .create-project
variables:
PROJECT: "ReducedCombinedConfig_FPGA2"
### Simulate
sim-ReducedCombinedConfig_FPGA1:
extends: .sim-project
dependencies:
- download
- create-ReducedCombinedConfig_FPGA1
variables:
PROJECT: "ReducedCombinedConfig_FPGA1"
sim-ReducedCombinedConfig_FPGA2:
extends: .sim-project
dependencies:
- download
- create-ReducedCombinedConfig_FPGA2
variables:
PROJECT: "ReducedCombinedConfig_FPGA2"
### Check simulation results
check-ReducedCombinedConfig_FPGA1:
extends: .check-project
dependencies:
- download
- sim-ReducedCombinedConfig_FPGA1
variables:
PROJECT: "ReducedCombinedConfig_FPGA1"
check-ReducedCombinedConfig_FPGA2:
extends: .check-project
dependencies:
- download
- sim-ReducedCombinedConfig_FPGA2
variables:
PROJECT: "ReducedCombinedConfig_FPGA2"
### Synthesize
synth-ReducedCombinedConfig_FPGA1:
extends: .synth-project
dependencies:
- download
- create-ReducedCombinedConfig_FPGA1
variables:
PROJECT: "ReducedCombinedConfig_FPGA1"
synth-ReducedCombinedConfig_FPGA2:
extends: .synth-project
dependencies:
- download
- create-ReducedCombinedConfig_FPGA2
variables:
PROJECT: "ReducedCombinedConfig_FPGA2"
### Implement
impl-ReducedCombinedConfig_FPGA1:
extends: .impl-project
dependencies:
- download
- create-ReducedCombinedConfig_FPGA1
- synth-ReducedCombinedConfig_FPGA1
variables:
PROJECT: "ReducedCombinedConfig_FPGA1"
impl-ReducedCombinedConfig_FPGA2:
extends: .impl-project
dependencies:
- download
- create-ReducedCombinedConfig_FPGA2
- synth-ReducedCombinedConfig_FPGA2
variables:
PROJECT: "ReducedCombinedConfig_FPGA2"
################################################################################