updated gtl_module_tpl.vhd

Author: herbberg

CHANGELOG.md

@@ -4,6 +4,16 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).
 
+## [v1.32.0] - 2025-05-12
+### Comment
+
+- updated gtl_module_tpl.vhd for Axo score output portsY
+
+### Changed
+- source files:
+  - ../packages/gt_mp7_core_pkg.vhd
+  - ../payload/gtl_module_tpl.vhd
+
 ## [v1.31.2] - 2025-04-14
 ### Comment
 

firmware/hdl/packages/gt_mp7_core_pkg.vhd

@@ -4,12 +4,12 @@
 -- actual versions:
 -- use "FRAME_VERSION" as mp7_ugt release fw version (used for tag name).
 
--- mp7_ugt (=FRAME_VERSION): v1.31.2
+-- mp7_ugt (=FRAME_VERSION): v1.32.0
 
 -- use "GT_VERSION" as mp7_ugt release fw version (used for tag name).
--- gt: v1.31.1
+-- gt: v1.32.0
 -- frame: v1.4.2 (see frame.vhd)
--- gtl: v1.24.2 (see gtl_module_tpl.vhd)
+-- gtl: v1.25.0 (see gtl_module_tpl.vhd)
 -- fdl: v1.4.1 (see fdl_module.vhd)
 
 -- HB 2024-09-04: v1.30.0 - Added vivado_fix_cells_tpl.tcl and constraints_fixed_cells.tcl to ../scripts.
@@ -37,6 +37,7 @@
 --
 -- gtl history:
 
+-- HB 2025-05-12: v1.25.0: Added output ports for AXO score value, moved "algo_pipeline_p" to VHDL Producer template.
 -- HB 2025-04-14: v1.24.2: Added AXOL1TL new model v5 payload.
 -- HB 2025-03-21: v1.24.1: Added AXOL1TL model v5 payload.
 -- HB 2025-01-07: v1.24.0: Implemented AXOL1TL model v5.
@@ -107,8 +108,8 @@ package gt_mp7_core_pkg is
 -- ==================================================================================================
 -- GT firmware version
     constant GT_MAJOR_VERSION      : integer range 0 to 255 := 1;
-    constant GT_MINOR_VERSION      : integer range 0 to 255 := 31;
-    constant GT_REV_VERSION        : integer range 0 to 255 := 2;
+    constant GT_MINOR_VERSION      : integer range 0 to 255 := 32;
+    constant GT_REV_VERSION        : integer range 0 to 255 := 0;
 	constant GT_VERSION : std_logic_vector(31 downto 0) := X"00" &
            std_logic_vector(to_unsigned(GT_MAJOR_VERSION, 8)) &
            std_logic_vector(to_unsigned(GT_MINOR_VERSION, 8)) &
@@ -119,8 +120,8 @@ package gt_mp7_core_pkg is
     constant FRAME_REV_VERSION        : integer range 0 to 255 := 2;
 -- GTL firmware (fix part) version
     constant GTL_FW_MAJOR_VERSION      : integer range 0 to 255 := 1;
-    constant GTL_FW_MINOR_VERSION      : integer range 0 to 255 := 24;
-    constant GTL_FW_REV_VERSION        : integer range 0 to 255 := 2;
+    constant GTL_FW_MINOR_VERSION      : integer range 0 to 255 := 25;
+    constant GTL_FW_REV_VERSION        : integer range 0 to 255 := 0;
 -- FDL firmware version
     constant FDL_FW_MAJOR_VERSION      : integer range 0 to 255 := 1;
     constant FDL_FW_MINOR_VERSION      : integer range 0 to 255 := 4;

firmware/hdl/payload/gtl_module_tpl.vhd

@@ -2,6 +2,7 @@
 -- Global Trigger Logic module.
 
 -- Version history:
+-- HB 2025-05-12: v1.25.0: Added output ports for AXO score value, moved "algo_pipeline_p" to VHDL Producer template.
 -- HB 2025-04-14: v1.24.2: Added AXOL1TL new model v5 payload.
 -- HB 2025-03-21: v1.24.1: Added AXOL1TL model v5 payload.
 -- HB 2025-01-07: v1.24.0: Implemented AXOL1TL model v5.
@@ -73,7 +74,12 @@ entity gtl_module is
     port(
         lhc_clk : in std_logic;
         gtl_data : in gtl_data_record;
-        algo_o : out std_logic_vector(NR_ALGOS-1 downto 0));
+        algo_o : out std_logic_vector(NR_ALGOS-1 downto 0);
+        axo_v1_score_o : out std_logic_vector(AXO_SCORE_WIDTH-1 downto 0) := "00"&"0000";
+        axo_v3_score_o : out std_logic_vector(AXO_SCORE_WIDTH-1 downto 0) := "00"&"0000";
+        axo_v4_score_o : out std_logic_vector(AXO_SCORE_WIDTH-1 downto 0) := "00"&"0000";
+        axo_v5_score_o : out std_logic_vector(AXO_SCORE_WIDTH-1 downto 0) := "00"&"0000"
+    );
 end gtl_module;
 
 architecture rtl of gtl_module is