Add chisel_cpu_diff demo

Author: 5265325

.gitignore

@@ -11,6 +11,7 @@
 !*.py
 !*.mk
 !*.bin
+!*.scala
 !Makefile
 !README
 !README.md

projects/chisel_cpu_diff/src/main/scala/Core.scala

@@ -0,0 +1,92 @@
+import chisel3._
+import chisel3.util.experimental._
+import difftest._
+
+class Core extends Module {
+  val io = IO(new Bundle {
+    val imem = new RomIO
+    val dmem = new RamIO
+  })
+
+  val fetch = Module(new InstFetch)
+  fetch.io.imem <> io.imem
+
+  val decode = Module(new Decode)
+  decode.io.inst := fetch.io.inst
+
+  val rf = Module(new RegFile)
+  rf.io.rs1_addr := decode.io.rs1_addr
+  rf.io.rs2_addr := decode.io.rs2_addr
+  rf.io.rd_addr := decode.io.rd_addr
+  rf.io.rd_en := decode.io.rd_en
+
+  val execution = Module(new Execution)
+  execution.io.opcode := decode.io.opcode
+  execution.io.in1 := Mux(decode.io.rs1_en, rf.io.rs1_data, 0.U)
+  execution.io.in2 := Mux(decode.io.rs2_en, rf.io.rs2_data, decode.io.imm)
+  execution.io.dmem <> io.dmem
+  rf.io.rd_data := execution.io.out
+
+  /* ----- Difftest ------------------------------ */
+
+  val dt_ic = Module(new DifftestInstrCommit)
+  dt_ic.io.clock    := clock
+  dt_ic.io.coreid   := 0.U
+  dt_ic.io.index    := 0.U
+  dt_ic.io.valid    := true.B
+  dt_ic.io.pc       := RegNext(fetch.io.pc)
+  dt_ic.io.instr    := RegNext(fetch.io.inst)
+  dt_ic.io.skip     := false.B
+  dt_ic.io.isRVC    := false.B
+  dt_ic.io.scFailed := false.B
+  dt_ic.io.wen      := RegNext(decode.io.rd_en)
+  dt_ic.io.wdata    := RegNext(execution.io.out)
+  dt_ic.io.wdest    := RegNext(decode.io.rd_addr)
+
+  val dt_ae = Module(new DifftestArchEvent)
+  dt_ae.io.clock        := clock
+  dt_ae.io.coreid       := 0.U
+  dt_ae.io.intrNO       := 0.U
+  dt_ae.io.cause        := 0.U
+  dt_ae.io.exceptionPC  := 0.U
+
+  val cycle_cnt = RegInit(0.U(64.W))
+  val instr_cnt = RegInit(0.U(64.W))
+
+  cycle_cnt := cycle_cnt + 1.U
+  instr_cnt := instr_cnt + 1.U
+
+  val rf_a0 = WireInit(0.U(64.W))
+  BoringUtils.addSink(rf_a0, "rf_a0")
+
+  val dt_te = Module(new DifftestTrapEvent)
+  dt_te.io.clock    := clock
+  dt_te.io.coreid   := 0.U
+  dt_te.io.valid    := (fetch.io.inst === "h0000006b".U)
+  dt_te.io.code     := rf_a0(2, 0)
+  dt_te.io.pc       := fetch.io.pc
+  dt_te.io.cycleCnt := cycle_cnt
+  dt_te.io.instrCnt := instr_cnt
+
+  val dt_cs = Module(new DifftestCSRState)
+  dt_cs.io.clock          := clock
+  dt_cs.io.coreid         := 0.U
+  dt_cs.io.priviledgeMode := 3.U  // Machine mode
+  dt_cs.io.mstatus        := 0.U
+  dt_cs.io.sstatus        := 0.U
+  dt_cs.io.mepc           := 0.U
+  dt_cs.io.sepc           := 0.U
+  dt_cs.io.mtval          := 0.U
+  dt_cs.io.stval          := 0.U
+  dt_cs.io.mtvec          := 0.U
+  dt_cs.io.stvec          := 0.U
+  dt_cs.io.mcause         := 0.U
+  dt_cs.io.scause         := 0.U
+  dt_cs.io.satp           := 0.U
+  dt_cs.io.mip            := 0.U
+  dt_cs.io.mie            := 0.U
+  dt_cs.io.mscratch       := 0.U
+  dt_cs.io.sscratch       := 0.U
+  dt_cs.io.mideleg        := 0.U
+  dt_cs.io.medeleg        := 0.U
+}

projects/chisel_cpu_diff/src/main/scala/Decode.scala

@@ -0,0 +1,43 @@
+import chisel3._
+import chisel3.util._
+import Instructions._
+
+class Decode extends Module {
+  val io = IO(new Bundle {
+    val inst = Input(UInt(32.W))
+    val rs1_addr = Output(UInt(5.W))
+    val rs1_en = Output(Bool())
+    val rs2_addr = Output(UInt(5.W))
+    val rs2_en = Output(Bool())
+    val rd_addr = Output(UInt(5.W))
+    val rd_en = Output(Bool())
+    val opcode = Output(UInt(8.W))
+    val imm = Output(UInt(64.W))
+  })
+
+  val inst = io.inst
+  val opcode = WireInit(UInt(8.W), 0.U)
+  val imm_i = Cat(Fill(53, inst(31)), inst(30, 20))
+
+  // Only example here, use your own control flow!
+  when (inst === ADDI) {
+    opcode := 1.U
+  }
+
+  io.rs1_addr := inst(19, 15)
+  io.rs2_addr := inst(24, 20)
+  io.rd_addr := inst(11, 7)
+  
+  io.rs1_en := false.B
+  io.rs2_en := false.B
+  io.rd_en := false.B
+
+  when (inst === ADDI) {
+    io.rs1_en := true.B
+    io.rs2_en := false.B
+    io.rd_en := true.B
+  }
+  
+  io.opcode := opcode
+  io.imm := imm_i
+}

projects/chisel_cpu_diff/src/main/scala/Execution.scala

@@ -0,0 +1,26 @@
+import chisel3._
+import chisel3.util._
+
+class Execution extends Module {
+  val io = IO(new Bundle {
+    val opcode = Input(UInt(8.W))
+    val in1 = Input(UInt(64.W))
+    val in2 = Input(UInt(64.W))
+    val out = Output(UInt(64.W))
+    val dmem = new RamIO
+  })
+
+  io.out := 0.U
+
+  // ADDI
+  when (io.opcode === 1.U) {
+    io.out := io.in1 + io.in2
+  }
+
+  io.dmem.en := false.B
+  io.dmem.addr := 0.U
+  io.dmem.wen := false.B
+  io.dmem.wdata := 0.U
+  io.dmem.wmask := 0.U
+
+}

projects/chisel_cpu_diff/src/main/scala/InstFetch.scala

@@ -0,0 +1,22 @@
+import chisel3._
+import chisel3.util._
+
+class InstFetch extends Module {
+  val io = IO(new Bundle {
+    val imem = new RomIO
+    val pc = Output(UInt(32.W))
+    val inst = Output(UInt(32.W))
+  })
+
+  val pc_en = RegInit(false.B)
+  pc_en := true.B
+
+  val pc = RegInit("h80000000".U(32.W))
+  pc := pc + 4.U
+
+  io.imem.en := true.B
+  io.imem.addr := pc.asUInt()
+
+  io.pc := Mux(pc_en, pc, 0.U)
+  io.inst := Mux(pc_en, io.imem.rdata(31, 0), 0.U)
+}

projects/chisel_cpu_diff/src/main/scala/Instructions.scala

@@ -0,0 +1,6 @@
+import chisel3._
+import chisel3.util._
+
+object Instructions {
+  def ADDI    = BitPat("b?????????????????000?????0010011")
+}

projects/chisel_cpu_diff/src/main/scala/Ram.scala

@@ -0,0 +1,48 @@
+import chisel3._
+import chisel3.util._
+
+class RomIO extends Bundle {
+  val en = Output(Bool())
+  val addr = Output(UInt(64.W))
+  val rdata = Input(UInt(64.W))
+}
+
+class RamIO extends RomIO {
+  val wdata = Output(UInt(64.W))
+  val wmask = Output(UInt(64.W))
+  val wen = Output(Bool())
+}
+
+class ram_2r1w extends BlackBox with HasBlackBoxResource {
+  val io = IO(new Bundle {
+    val clk = Input(Clock())
+    val imem_en = Input(Bool())
+    val imem_addr = Input(UInt(64.W))
+    val imem_data = Output(UInt(32.W))
+    val dmem_en = Input(Bool())
+    val dmem_addr = Input(UInt(64.W))
+    val dmem_rdata = Output(UInt(64.W))
+    val dmem_wdata = Input(UInt(64.W))
+    val dmem_wmask = Input(UInt(64.W))
+    val dmem_wen = Input(Bool())
+  })
+  addResource("/vsrc/ram_2r1w.v")
+}
+
+class Ram2r1w extends Module {
+  val io = IO(new Bundle {
+    val imem = Flipped(new RomIO)
+    val dmem = Flipped(new RamIO)
+  })
+  val mem = Module(new ram_2r1w)
+  mem.io.clk        := clock
+  mem.io.imem_en    := io.imem.en
+  mem.io.imem_addr  := io.imem.addr
+  io.imem.rdata     := mem.io.imem_data
+  mem.io.dmem_en    := io.dmem.en
+  mem.io.dmem_addr  := io.dmem.addr
+  io.dmem.rdata     := mem.io.dmem_rdata
+  mem.io.dmem_wdata := io.dmem.wdata
+  mem.io.dmem_wmask := io.dmem.wmask
+  mem.io.dmem_wen   := io.dmem.wen
+}

projects/chisel_cpu_diff/src/main/scala/RegFile.scala

@@ -0,0 +1,31 @@
+import chisel3._
+import chisel3.util.experimental._
+import difftest._
+
+class RegFile extends Module {
+  val io = IO(new Bundle {
+    val rs1_addr = Input(UInt(5.W))
+    val rs2_addr = Input(UInt(5.W))
+    val rs1_data = Output(UInt(64.W))
+    val rs2_data = Output(UInt(64.W))
+    val rd_addr = Input(UInt(5.W))
+    val rd_data = Input(UInt(64.W))
+    val rd_en = Input(Bool())
+  })
+
+  val rf = RegInit(VecInit(Seq.fill(32)(0.U(64.W))))
+
+  when (io.rd_en && (io.rd_addr =/= 0.U)) {
+    rf(io.rd_addr) := io.rd_data;
+  }
+
+  io.rs1_data := Mux((io.rs1_addr =/= 0.U), rf(io.rs1_addr), 0.U)
+  io.rs2_data := Mux((io.rs2_addr =/= 0.U), rf(io.rs2_addr), 0.U)
+
+  val dt_ar = Module(new DifftestArchIntRegState)
+  dt_ar.io.clock  := clock
+  dt_ar.io.coreid := 0.U
+  dt_ar.io.gpr    := rf
+
+  BoringUtils.addSource(rf(10), "rf_a0")
+}

projects/chisel_cpu_diff/src/main/scala/SimTop.scala

@@ -0,0 +1,22 @@
+import chisel3._
+import chisel3.util._
+import difftest._
+
+class SimTop extends Module {
+  val io = IO(new Bundle {
+    val logCtrl = new LogCtrlIO
+    val perfInfo = new PerfInfoIO
+    val uart = new UARTIO
+  })
+
+  val core = Module(new Core)
+
+  val mem = Module(new Ram2r1w)
+  mem.io.imem <> core.io.imem
+  mem.io.dmem <> core.io.dmem
+
+  io.uart.out.valid := false.B
+  io.uart.out.ch := 0.U
+  io.uart.in.valid := false.B
+
+}

projects/chisel_cpu_diff/src/main/scala/TopMain.scala

@@ -0,0 +1,3 @@
+object TopMain extends App {
+  (new chisel3.stage.ChiselStage).execute(args, Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new SimTop())))
+}