Update difftest

Author: 5265325

README.md

@@ -115,8 +115,8 @@ Enter the test cycle:
 ```shell
 # 编译仿真
 ./build.sh -e cpu_diff -d -b -s -a "-i inst_diff.bin"
-# 编译仿真，并从CPU上报至difftest的时钟周期0开始输出波形
-./build.sh -e cpu_diff -d -b -s -a "-i inst_diff.bin --dump-wave -b 0" -m "EMU_TRACE=1"
+# 编译仿真，并从CPU上报至difftest的时钟周期0开始输出波形至wave.vcd文件
+./build.sh -e cpu_diff -d -b -s -a "-i inst_diff.bin --wave-path=wave.vcd --dump-wave -b 0" -m "EMU_TRACE=1"
 ```
 
 仿真程序运行后，终端将打印绿色的提示内容`HIT GOOD TRAP at pc = 0x8000000c`。说明程序运行到自定义的`0x6b`指令，并且此时存放错误码的`a0`寄存器的值为0，即程序按照预期结果成功退出。关于`0x6b`自定义指令作用，可参考[讲座-AM运行环境介绍](https://oscpu.github.io/ysyx/events/events.html?EID=2021-07-13_AM_Difftest)。如果指定输出波形，将在`projects/cpu_diff/build/`路径下生成`.vcd`波形文件。
@@ -126,7 +126,7 @@ Enter the test cycle:
 `projects/cpu_diff`目录下存放了通过`AXI总线`接入`香山difftest框架`的`verilog`版本单周期`RISC-V`CPU例程源码，源码实现了`RV64I`指令`addi`和`AXI总线`读逻辑。可以使用下面的命令编译和仿真。
 
 ```shell
-./build.sh -e cpu_axi_diff -d -s -a "-i inst_diff.bin --dump-wave -b 0" -m "EMU_TRACE=1 WITH_DRAMSIM3=1" -b
+./build.sh -e cpu_axi_diff -d -s -a "-i inst_diff.bin --wave-path=wave.vcd --dump-wave -b 0" -m "EMU_TRACE=1 WITH_DRAMSIM3=1" -b
 ```
 
 ### chisel_cpu_diff

libraries/difftest

@@ -158,6 +158,7 @@ DifftestInstrCommit DifftestInstrCommit(
   .valid              (cmt_valid),
   .pc                 (cmt_pc),
   .instr              (cmt_inst),
+  .special            (0),
   .skip               (0),
   .isRVC              (0),
   .scFailed           (0),

projects/cpu_axi_diff/vsrc/cpu.v

@@ -148,6 +148,7 @@ DifftestInstrCommit DifftestInstrCommit(
   .valid              (cmt_valid),
   .pc                 (cmt_pc),
   .instr              (cmt_inst),
+  .special            (0),
   .skip               (0),
   .isRVC              (0),
   .scFailed           (0),