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dwiklemarijnh
dwikle
authored and
marijnh
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[verilog mode] Rewrite
Conflicts: mode/verilog/verilog.js
1 parent 2a49b17 commit 1e1ae42

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‎mode/index.html‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ <h2>Language modes</h2>
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<li><a href="vb/index.html">VB.NET</a></li>
109109
<li><a href="vbscript/index.html">VBScript</a></li>
110110
<li><a href="velocity/index.html">Velocity</a></li>
111-
<li><a href="verilog/index.html">Verilog</a></li>
111+
<li><a href="verilog/index.html">Verilog/SystemVerilog</a></li>
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<li><a href="xml/index.html">XML/HTML</a></li>
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<li><a href="xquery/index.html">XQuery</a></li>
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<li><a href="yaml/index.html">YAML</a></li>

‎mode/meta.js‎

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Original file line numberDiff line numberDiff line change
@@ -79,6 +79,7 @@ CodeMirror.modeInfo = [
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{name: 'MariaDB', mime: 'text/x-mariadb', mode: 'sql'},
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{name: 'sTeX', mime: 'text/x-stex', mode: 'stex'},
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{name: 'LaTeX', mime: 'text/x-latex', mode: 'stex'},
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{name: 'SystemVerilog', mime: 'text/x-systemverilog', mode: 'verilog'},
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{name: 'Tcl', mime: 'text/x-tcl', mode: 'tcl'},
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{name: 'TiddlyWiki ', mime: 'text/x-tiddlywiki', mode: 'tiddlywiki'},
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{name: 'Tiki wiki', mime: 'text/tiki', mode: 'tiki'},

‎mode/verilog/index.html‎

Lines changed: 89 additions & 101 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,14 @@
11
<!doctype html>
22

3-
<title>CodeMirror: Verilog mode</title>
3+
<title>CodeMirror: Verilog/SystemVerilog mode</title>
44
<meta charset="utf-8"/>
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<link rel=stylesheet href="../../doc/docs.css">
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<link rel="stylesheet" href="../../lib/codemirror.css">
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<script src="../../lib/codemirror.js"></script>
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<script src="../../addon/edit/matchbrackets.js"></script>
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<script src="verilog.js"></script>
10-
<style>.CodeMirror {border: 2px inset #dee;}</style>
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<style type="text/css">.CodeMirror {border-top: 1px solid black; border-bottom: 1px solid black;}</style>
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<div id=nav>
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<a href="http://codemirror.net"><img id=logo src="../../doc/logo.png"></a>
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@@ -18,115 +19,102 @@
1819
</ul>
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<ul>
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<li><a href="../index.html">Language modes</a>
21-
<li><a class=active href="#">Verilog</a>
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<li><a class=active href="#">Verilog/SystemVerilog</a>
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</ul>
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</div>
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2526
<article>
26-
<h2>Verilog mode</h2>
27-
<form><textarea id="code" name="code">
28-
/* Verilog demo code */
27+
<h2>SystemVerilog mode</h2>
2928

30-
module butterfly
31-
#(
32-
parameter WIDTH = 32,
33-
parameter MWIDTH = 1
34-
)
35-
(
36-
input wire clk,
37-
input wire rst_n,
38-
// m_in contains data that passes through this block with no change.
39-
input wire [MWIDTH-1:0] m_in,
40-
// The twiddle factor.
41-
input wire signed [WIDTH-1:0] w,
42-
// XA
43-
input wire signed [WIDTH-1:0] xa,
44-
// XB
45-
input wire signed [WIDTH-1:0] xb,
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// Set to 1 when new data is present on inputs.
47-
input wire x_nd,
48-
// delayed version of m_in.
49-
output reg [MWIDTH-1:0] m_out,
50-
// YA = XA + W*XB
51-
// YB = XA - W*XB
52-
output wire signed [WIDTH-1:0] ya,
53-
output wire signed [WIDTH-1:0] yb,
54-
output reg y_nd,
55-
output reg error
56-
);
29+
<div><textarea id="code" name="code">
30+
// Literals
31+
1'b0
32+
1'bx
33+
1'bz
34+
16'hDC78
35+
'hdeadbeef
36+
'b0011xxzz
37+
1234
38+
32'd5678
39+
3.4e6
40+
-128.7
5741

58-
// Set wire to the real and imag parts for convenience.
59-
wire signed [WIDTH/2-1:0] xa_re;
60-
wire signed [WIDTH/2-1:0] xa_im;
61-
assign xa_re = xa[WIDTH-1:WIDTH/2];
62-
assign xa_im = xa[WIDTH/2-1:0];
63-
wire signed [WIDTH/2-1: 0] ya_re;
64-
wire signed [WIDTH/2-1: 0] ya_im;
65-
assign ya = {ya_re, ya_im};
66-
wire signed [WIDTH/2-1: 0] yb_re;
67-
wire signed [WIDTH/2-1: 0] yb_im;
68-
assign yb = {yb_re, yb_im};
42+
// Macro definition
43+
`define BUS_WIDTH = 8;
6944

70-
// Delayed stuff.
71-
reg signed [WIDTH/2-1:0] xa_re_z;
72-
reg signed [WIDTH/2-1:0] xa_im_z;
73-
// Output of multiplier
74-
wire signed [WIDTH-1:0] xbw;
75-
wire signed [WIDTH/2-1:0] xbw_re;
76-
wire signed [WIDTH/2-1:0] xbw_im;
77-
assign xbw_re = xbw[WIDTH-1:WIDTH/2];
78-
assign xbw_im = xbw[WIDTH/2-1:0];
79-
// Do summing
80-
// I don't think we should get overflow here because of the
81-
// size of the twiddle factors.
82-
// If we do testing should catch it.
83-
assign ya_re = xa_re_z + xbw_re;
84-
assign ya_im = xa_im_z + xbw_im;
85-
assign yb_re = xa_re_z - xbw_re;
86-
assign yb_im = xa_im_z - xbw_im;
87-
88-
// Create the multiply module.
89-
multiply_complex #(WIDTH) multiply_complex_0
90-
(.clk(clk),
91-
.rst_n(rst_n),
92-
.x(xb),
93-
.y(w),
94-
.z(xbw)
95-
);
45+
// Module definition
46+
module block(
47+
input clk,
48+
input rst_n,
49+
input [`BUS_WIDTH-1:0] data_in,
50+
output [`BUS_WIDTH-1:0] data_out
51+
);
52+
53+
always @(posedge clk or negedge rst_n) begin
9654

97-
always @ (posedge clk)
98-
begin
99-
if (!rst_n)
100-
begin
101-
y_nd <= 1'b0;
102-
error <= 1'b0;
103-
end
104-
else
105-
begin
106-
// Set delay for x_nd_old and m.
107-
y_nd <= x_nd;
108-
m_out <= m_in;
109-
if (x_nd)
110-
begin
111-
xa_re_z <= xa_re/2;
112-
xa_im_z <= xa_im/2;
113-
end
114-
end
55+
if (~rst_n) begin
56+
data_out <= 8'b0;
57+
end else begin
58+
data_out <= data_in;
11559
end
116-
60+
61+
if (~rst_n)
62+
data_out <= 8'b0;
63+
else
64+
data_out <= data_in;
65+
66+
if (~rst_n)
67+
begin
68+
data_out <= 8'b0;
69+
end
70+
else
71+
begin
72+
data_out <= data_in;
73+
end
74+
75+
end
76+
11777
endmodule
118-
</textarea></form>
11978

120-
<script>
121-
var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
122-
lineNumbers: true,
123-
mode: "text/x-verilog"
124-
});
125-
</script>
79+
// Class definition
80+
class test;
81+
82+
/**
83+
* Sum two integers
84+
*/
85+
function int sum(int a, int b);
86+
int result = a + b;
87+
string msg = $sformatf("%d + %d = %d", a, b, result);
88+
$display(msg);
89+
return result;
90+
endfunction
91+
92+
task delay(int num_cycles);
93+
repeat(num_cycles) #1;
94+
endtask
95+
96+
endclass
97+
98+
</textarea></div>
12699

127-
<p>Simple mode that tries to handle Verilog-like languages as well as it
128-
can. Takes one configuration parameters: <code>keywords</code>, an
129-
object whose property names are the keywords in the language.</p>
100+
<script>
101+
var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
102+
lineNumbers: true,
103+
matchBrackets: true,
104+
mode: {
105+
name: "verilog",
106+
noIndentKeywords: ["package"]
107+
}
108+
});
109+
</script>
110+
111+
<p>
112+
Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800).
113+
<h2>Configuration options:</h2>
114+
<ul>
115+
<li><strong>noIndentKeywords</strong> - List of keywords which should not cause identation to increase. E.g. ["package", "module"]. Default: None</li>
116+
</ul>
117+
</p>
130118

131-
<p><strong>MIME types defined:</strong> <code>text/x-verilog</code> (Verilog code).</p>
132-
</article>
119+
<p><strong>MIME types defined:</strong> <code>text/x-verilog</code> and <code>text/x-systemverilog</code>.</p>
120+
</article>

‎mode/verilog/test.js‎

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@@ -0,0 +1,114 @@
1+
(function() {
2+
var mode = CodeMirror.getMode({indentUnit: 4}, "verilog");
3+
function MT(name) { test.mode(name, mode, Array.prototype.slice.call(arguments, 1)); }
4+
5+
MT("Binary literals",
6+
"[number 1'b0]",
7+
"[number 1'b1]",
8+
"[number 1'bx]",
9+
"[number 1'bz]",
10+
"[number 1'bX]",
11+
"[number 1'bZ]",
12+
"[number 1'B0]",
13+
"[number 1'B1]",
14+
"[number 1'Bx]",
15+
"[number 1'Bz]",
16+
"[number 1'BX]",
17+
"[number 1'BZ]",
18+
"[number 1'b0]",
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"[number 1'b1]",
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"[number 2'b01]",
21+
"[number 2'bxz]",
22+
"[number 2'b11]",
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"[number 2'b10]",
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"[number 2'b1Z]",
25+
"[number 12'b0101_0101_0101]",
26+
"[number 1'b 0]",
27+
"[number 'b0101]"
28+
);
29+
30+
MT("Octal literals",
31+
"[number 3'o7]",
32+
"[number 3'O7]",
33+
"[number 3'so7]",
34+
"[number 3'SO7]"
35+
);
36+
37+
MT("Decimal literals",
38+
"[number 0]",
39+
"[number 1]",
40+
"[number 7]",
41+
"[number 123_456]",
42+
"[number 'd33]",
43+
"[number 8'd255]",
44+
"[number 8'D255]",
45+
"[number 8'sd255]",
46+
"[number 8'SD255]",
47+
"[number 32'd123]",
48+
"[number 32 'd123]",
49+
"[number 32 'd 123]"
50+
);
51+
52+
MT("Hex literals",
53+
"[number 4'h0]",
54+
"[number 4'ha]",
55+
"[number 4'hF]",
56+
"[number 4'hx]",
57+
"[number 4'hz]",
58+
"[number 4'hX]",
59+
"[number 4'hZ]",
60+
"[number 32'hdc78]",
61+
"[number 32'hDC78]",
62+
"[number 32 'hDC78]",
63+
"[number 32'h DC78]",
64+
"[number 32 'h DC78]",
65+
"[number 32'h44x7]",
66+
"[number 32'hFFF?]"
67+
);
68+
69+
MT("Real number literals",
70+
"[number 1.2]",
71+
"[number 0.1]",
72+
"[number 2394.26331]",
73+
"[number 1.2E12]",
74+
"[number 1.2e12]",
75+
"[number 1.30e-2]",
76+
"[number 0.1e-0]",
77+
"[number 23E10]",
78+
"[number 29E-2]",
79+
"[number 236.123_763_e-12]"
80+
);
81+
82+
MT("Operators",
83+
"[meta ^]"
84+
);
85+
86+
MT("Keywords",
87+
"[keyword logic]",
88+
"[keyword logic] [variable foo]",
89+
"[keyword reg] [variable abc]"
90+
);
91+
92+
MT("Variables",
93+
"[variable _leading_underscore]",
94+
"[variable _if]",
95+
"[number 12] [variable foo]",
96+
"[variable foo] [number 14]"
97+
);
98+
99+
MT("Tick defines",
100+
"[def `FOO]",
101+
"[def `foo]",
102+
"[def `FOO_bar]"
103+
);
104+
105+
MT("System calls",
106+
"[meta $display]",
107+
"[meta $vpi_printf]"
108+
);
109+
110+
MT("Line comment", "[comment // Hello world]");
111+
112+
113+
114+
})();

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