[RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061)

he spimm operand is an immediate whose only 4-5th bit could be setted
and not based on rlist operand

Author: yetingk

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -462,10 +462,8 @@ static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
   return MCDisassembler::Success;
 }
 
-// spimm is based on rlist now.
 static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
                                     uint64_t Address, const void *Decoder) {
-  // TODO: check if spimm matches rlist
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

@@ -69,7 +69,7 @@ def spimm : Operand<OtherVT> {
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
-    return isShiftedUInt<5, 4>(Imm);
+    return isShiftedUInt<2, 4>(Imm);
   }];
 }