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1 parent ddb3b3f commit db66b5eCopy full SHA for db66b5e
xml/issue4390.xml
@@ -18,7 +18,7 @@ intuitive spelling:
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simd::vec<complex<double>> sc1 ({-1.0, 0.5}); // <span style="color:#C80000;font-weight:bold">current ill-formed</span>
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simd::vec<complex<double>> sc2 = {{-1.0, 0.5}}; // <span style="color:#C80000;font-weight:bold">current ill-formed</span></pre>
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-<note>Reflector pool 2025-10-22; Status changed: New → LEWG writh priority 4.</note>
+<note>2025-10-22; Reflector poll. Status changed: New → LEWG with priority 4.</note>
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<p>
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This narrows design space wrt using braces for initialization
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