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[AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (llvm#177525)
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4 files changed

+159
-28
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4 files changed

+159
-28
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1058,7 +1058,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
10581058
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}})
10591059
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}});
10601060

1061-
addRulesForGOpcs({G_FLDEXP}, Standard)
1061+
addRulesForGOpcs({G_FLDEXP, G_STRICT_FLDEXP}, Standard)
10621062
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}})
10631063
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
10641064
.Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}})

‎llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll‎

Lines changed: 87 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,11 @@
66
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
77
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
88

9-
; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
10-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
11-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
12-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
13-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
9+
; XUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
10+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
11+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
12+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
13+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
1414

1515
; define half @test_ldexp_f16_i16(ptr addrspace(1) %out, half %a, i16 %b) #0 {
1616
; %result = call half @llvm.experimental.constrained.ldexp.f16.i16(half %a, i16 %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -287,11 +287,12 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a,
287287
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7fff
288288
; GFX9-GISEL-NEXT: v_med3_i32 v4, v4, v0, v1
289289
; GFX9-GISEL-NEXT: v_med3_i32 v5, v5, v0, v1
290+
; GFX9-GISEL-NEXT: v_med3_i32 v0, v6, v0, v1
290291
; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v4, v2, v4
291292
; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
292-
; GFX9-GISEL-NEXT: v_med3_i32 v0, v6, v0, v1
293293
; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v1, v3, v0
294294
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v4
295+
; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
295296
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
296297
;
297298
; GFX11-GISEL-TRUE16-LABEL: test_ldexp_v3f16_v3i32:
@@ -312,18 +313,21 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a,
312313
; GFX11-GISEL-FAKE16: ; %bb.0:
313314
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
314315
; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7fff
315-
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
316+
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
316317
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v4, v0
317-
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
318-
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v5, 0xffff8000, v5, v0
319-
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v2, v1
320-
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
321-
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v2, v4, v5
322318
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v4, 0xffff8000, v6, v0
319+
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
320+
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v5, v0
321+
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v2, v1
322+
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
323+
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v2, v3, v4
324+
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v6, v0
325+
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
323326
; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
324-
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
325-
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v1
326-
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v3, v4
327+
; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
328+
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
329+
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
330+
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2
327331
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
328332
%result = call <3 x half> @llvm.experimental.constrained.ldexp.v3f16.v3i32(<3 x half> %a, <3 x i32> %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
329333
ret <3 x half> %result
@@ -482,6 +486,74 @@ define <4 x half> @test_ldexp_v4f16_v4i32(ptr addrspace(1) %out, <4 x half> %a,
482486
ret <4 x half> %result
483487
}
484488

489+
define amdgpu_ps half @s_test_ldexp_f16_i32(half inreg %a, i32 inreg %b) #0 {
490+
; GFX8-SDAG-LABEL: s_test_ldexp_f16_i32:
491+
; GFX8-SDAG: ; %bb.0:
492+
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0xffff8000
493+
; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, 0x7fff
494+
; GFX8-SDAG-NEXT: v_med3_i32 v0, s1, v0, v1
495+
; GFX8-SDAG-NEXT: v_ldexp_f16_e32 v0, s0, v0
496+
; GFX8-SDAG-NEXT: ; return to shader part epilog
497+
;
498+
; GFX9-SDAG-LABEL: s_test_ldexp_f16_i32:
499+
; GFX9-SDAG: ; %bb.0:
500+
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0xffff8000
501+
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x7fff
502+
; GFX9-SDAG-NEXT: v_med3_i32 v0, s1, v0, v1
503+
; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, s0, v0
504+
; GFX9-SDAG-NEXT: ; return to shader part epilog
505+
;
506+
; GFX11-SDAG-TRUE16-LABEL: s_test_ldexp_f16_i32:
507+
; GFX11-SDAG-TRUE16: ; %bb.0:
508+
; GFX11-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, 0x7fff
509+
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
510+
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, s1, v0
511+
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, s0, v0.l
512+
; GFX11-SDAG-TRUE16-NEXT: ; return to shader part epilog
513+
;
514+
; GFX11-SDAG-FAKE16-LABEL: s_test_ldexp_f16_i32:
515+
; GFX11-SDAG-FAKE16: ; %bb.0:
516+
; GFX11-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7fff
517+
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
518+
; GFX11-SDAG-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, s1, v0
519+
; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e32 v0, s0, v0
520+
; GFX11-SDAG-FAKE16-NEXT: ; return to shader part epilog
521+
;
522+
; GFX8-GISEL-LABEL: s_test_ldexp_f16_i32:
523+
; GFX8-GISEL: ; %bb.0:
524+
; GFX8-GISEL-NEXT: s_max_i32 s1, s1, 0xffff8000
525+
; GFX8-GISEL-NEXT: s_min_i32 s1, s1, 0x7fff
526+
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s1
527+
; GFX8-GISEL-NEXT: v_ldexp_f16_e32 v0, s0, v0
528+
; GFX8-GISEL-NEXT: ; return to shader part epilog
529+
;
530+
; GFX9-GISEL-LABEL: s_test_ldexp_f16_i32:
531+
; GFX9-GISEL: ; %bb.0:
532+
; GFX9-GISEL-NEXT: s_max_i32 s1, s1, 0xffff8000
533+
; GFX9-GISEL-NEXT: s_min_i32 s1, s1, 0x7fff
534+
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1
535+
; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, s0, v0
536+
; GFX9-GISEL-NEXT: ; return to shader part epilog
537+
;
538+
; GFX11-GISEL-TRUE16-LABEL: s_test_ldexp_f16_i32:
539+
; GFX11-GISEL-TRUE16: ; %bb.0:
540+
; GFX11-GISEL-TRUE16-NEXT: s_max_i32 s1, s1, 0xffff8000
541+
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
542+
; GFX11-GISEL-TRUE16-NEXT: s_min_i32 s1, s1, 0x7fff
543+
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, s0, s1
544+
; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog
545+
;
546+
; GFX11-GISEL-FAKE16-LABEL: s_test_ldexp_f16_i32:
547+
; GFX11-GISEL-FAKE16: ; %bb.0:
548+
; GFX11-GISEL-FAKE16-NEXT: s_max_i32 s1, s1, 0xffff8000
549+
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
550+
; GFX11-GISEL-FAKE16-NEXT: s_min_i32 s1, s1, 0x7fff
551+
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, s0, s1
552+
; GFX11-GISEL-FAKE16-NEXT: ; return to shader part epilog
553+
%result = call half @llvm.experimental.constrained.ldexp.f16.i32(half %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
554+
ret half %result
555+
}
556+
485557
declare half @llvm.experimental.constrained.ldexp.f16.i16(half, i16, metadata, metadata) #1
486558
declare half @llvm.experimental.constrained.ldexp.f16.i32(half, i32, metadata, metadata) #1
487559
declare <2 x half> @llvm.experimental.constrained.ldexp.v2f16.v2i16(<2 x half>, <2 x i16>, metadata, metadata) #1

‎llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll‎

Lines changed: 31 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@
44
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
55
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG %s
66

7-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
8-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
9-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
10-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s
7+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
8+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
9+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
10+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s
1111

1212
; define float @test_ldexp_f32_i16(ptr addrspace(1) %out, float %a, i16 %b) #0 {
1313
; %result = call float @llvm.experimental.constrained.ldexp.f32.i16(float %a, i16 %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -236,6 +236,33 @@ define <4 x float> @test_ldexp_v4f32_v4i32(ptr addrspace(1) %out, <4 x float> %a
236236
ret <4 x float> %result
237237
}
238238

239+
define amdgpu_ps float @s_test_ldexp_f32_i32(float inreg %a, i32 inreg %b) #0 {
240+
; GFX6-LABEL: s_test_ldexp_f32_i32:
241+
; GFX6: ; %bb.0:
242+
; GFX6-NEXT: v_mov_b32_e32 v0, s1
243+
; GFX6-NEXT: v_ldexp_f32_e32 v0, s0, v0
244+
; GFX6-NEXT: ; return to shader part epilog
245+
;
246+
; GFX8-LABEL: s_test_ldexp_f32_i32:
247+
; GFX8: ; %bb.0:
248+
; GFX8-NEXT: v_mov_b32_e32 v0, s1
249+
; GFX8-NEXT: v_ldexp_f32 v0, s0, v0
250+
; GFX8-NEXT: ; return to shader part epilog
251+
;
252+
; GFX9-LABEL: s_test_ldexp_f32_i32:
253+
; GFX9: ; %bb.0:
254+
; GFX9-NEXT: v_mov_b32_e32 v0, s1
255+
; GFX9-NEXT: v_ldexp_f32 v0, s0, v0
256+
; GFX9-NEXT: ; return to shader part epilog
257+
;
258+
; GFX11-LABEL: s_test_ldexp_f32_i32:
259+
; GFX11: ; %bb.0:
260+
; GFX11-NEXT: v_ldexp_f32 v0, s0, s1
261+
; GFX11-NEXT: ; return to shader part epilog
262+
%result = call float @llvm.experimental.constrained.ldexp.f32.i32(float %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
263+
ret float %result
264+
}
265+
239266
declare float @llvm.experimental.constrained.ldexp.f32.i16(float, i16, metadata, metadata) #1
240267
declare float @llvm.experimental.constrained.ldexp.f32.i32(float, i32, metadata, metadata) #1
241268
declare <2 x float> @llvm.experimental.constrained.ldexp.v2f32.v2i16(<2 x float>, <2 x i16>, metadata, metadata) #1

‎llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll‎

Lines changed: 40 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@
44
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
55
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG %s
66

7-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
8-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
9-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
10-
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s
7+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
8+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
9+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
10+
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s
1111

1212
; define double @test_ldexp_f64_i16(ptr addrspace(1) %out, double %a, i16 %b) #0 {
1313
; %result = call double @llvm.experimental.constrained.ldexp.f64.i16(double %a, i16 %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -65,6 +65,42 @@ define <4 x double> @test_ldexp_v4f64_v4i32(ptr addrspace(1) %out, <4 x double>
6565
ret <4 x double> %result
6666
}
6767

68+
define amdgpu_ps double @s_test_ldexp_f64_i32(double inreg %a, i32 inreg %b) #0 {
69+
; GFX6-LABEL: s_test_ldexp_f64_i32:
70+
; GFX6: ; %bb.0:
71+
; GFX6-NEXT: v_mov_b32_e32 v0, s2
72+
; GFX6-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
73+
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
74+
; GFX6-NEXT: v_readfirstlane_b32 s1, v1
75+
; GFX6-NEXT: ; return to shader part epilog
76+
;
77+
; GFX8-LABEL: s_test_ldexp_f64_i32:
78+
; GFX8: ; %bb.0:
79+
; GFX8-NEXT: v_mov_b32_e32 v0, s2
80+
; GFX8-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
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; GFX8-NEXT: v_readfirstlane_b32 s0, v0
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; GFX8-NEXT: v_readfirstlane_b32 s1, v1
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; GFX8-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: s_test_ldexp_f64_i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, s2
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; GFX9-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
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; GFX9-NEXT: v_readfirstlane_b32 s0, v0
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; GFX9-NEXT: v_readfirstlane_b32 s1, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: s_test_ldexp_f64_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_ldexp_f64 v[0:1], s[0:1], s2
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-NEXT: v_readfirstlane_b32 s1, v1
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; GFX11-NEXT: ; return to shader part epilog
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%result = call double @llvm.experimental.constrained.ldexp.f64.i32(double %a, i32 %b, metadata !"round.dynamic", metadata !"fpexcept.strict")
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ret double %result
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}
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declare double @llvm.experimental.constrained.ldexp.f64.i16(double, i16, metadata, metadata) #1
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declare double @llvm.experimental.constrained.ldexp.f64.i32(double, i32, metadata, metadata) #1
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declare <2 x double> @llvm.experimental.constrained.ldexp.v2f64.v2i16(<2 x double>, <2 x i16>, metadata, metadata) #1
@@ -75,15 +111,11 @@ declare <4 x double> @llvm.experimental.constrained.ldexp.v4f64.v4i32(<4 x doubl
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attributes #0 = { strictfp }
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attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite) }
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
78-
; GFX11: {{.*}}
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; GFX11-GISEL: {{.*}}
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; GFX11-SDAG: {{.*}}
81-
; GFX6: {{.*}}
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; GFX6-GISEL: {{.*}}
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; GFX6-SDAG: {{.*}}
84-
; GFX8: {{.*}}
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; GFX8-GISEL: {{.*}}
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; GFX8-SDAG: {{.*}}
87-
; GFX9: {{.*}}
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; GFX9-GISEL: {{.*}}
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; GFX9-SDAG: {{.*}}

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