Formatting

Author: satiscugcat

testable-simd-models/src/core_arch/x86/models/avx2.rs

@@ -916,8 +916,6 @@ pub fn _mm256_and_si256(a: __m256i, b: __m256i) -> __m256i {
     simd_and(BitVec::to_i64x4(a), BitVec::to_i64x4(b)).into()
 }
 
-
-
 /// Computes the bitwise NOT of 256 bits (representing integer data)
 /// in `a` and then AND with `b`.
 ///
@@ -2137,8 +2135,6 @@ pub fn _mm256_srli_si256<const IMM8: i32>(a: __m256i) -> __m256i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_bsrli_epi128)
 
 pub fn _mm256_bsrli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
-
-    
     const fn mask(shift: i32, i: u32) -> u64 {
         let shift = shift as u32 & 0xff;
         if shift > 15 || (15 - (i % 16)) < shift {
@@ -2147,7 +2143,7 @@ pub fn _mm256_bsrli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
             (32 + (i + shift)) as u64
         }
     }
-    
+
     let a = BitVec::to_i8x32(a);
     let r: i8x32 = simd_shuffle(
         i8x32::from_fn(|_| 0),
@@ -2187,7 +2183,7 @@ pub fn _mm256_bsrli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
             mask(IMM8, 31),
         ],
     );
-    
+
     r.into()
 }
 

testable-simd-models/src/core_arch/x86/specs/avx2.rs

@@ -12,9 +12,11 @@ pub fn _mm256_bsrli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
     let a = BitVec::to_i128x2(a);
     let a = i128x2::from_fn(|i| {
         let tmp = IMM8 % 256;
-        if tmp > 15 {0} else {
+        if tmp > 15 {
+            0
+        } else {
             ((a[i] as u128) >> (tmp * 8)) as i128
-	}
+        }
     });
     BitVec::from_i128x2(a)
 }

testable-simd-models/src/core_arch/x86/tests/avx.rs

@@ -54,15 +54,14 @@ fn _mm256_testz_si256() {
 
     for _ in 0..n {
         let a: BitVec<256> = BitVec::random();
-	let b: BitVec<256> = BitVec::random();
+        let b: BitVec<256> = BitVec::random();
         assert_eq!(
             super::super::models::avx::_mm256_testz_si256(a.into(), b.into()),
             unsafe { upstream::_mm256_testz_si256(a.into(), b.into()) }
         );
     }
 }
 
-
 mk!(_mm256_setzero_ps());
 mk!(_mm256_setzero_si256());
 mk!(_mm256_set_epi8(