Formatting

Author: satiscugcat

testable-simd-models/src/abstractions/bitvec.rs

@@ -4,7 +4,6 @@ use super::funarr::*;
 
 use std::fmt::Formatter;
 
-
 /// A fixed-size bit vector type.
 ///
 /// `BitVec<N>` is a specification-friendly, fixed-length bit vector that internally
@@ -154,4 +153,3 @@ impl<const N: u64> BitVec<N> {
         self.0.fold(init, f)
     }
 }
-

testable-simd-models/src/abstractions/simd.rs

@@ -2,13 +2,11 @@
 //!
 //! Operations are defined on FunArrs.
 
-
-
 use crate::abstractions::{bit::MachineInteger, funarr::FunArray};
 
 pub mod int_vec_interp {
-    use crate::abstractions::bitvec::*;
     use crate::abstractions::bit::MachineInteger;
+    use crate::abstractions::bitvec::*;
     use crate::abstractions::funarr::*;
 
     #[allow(dead_code)]
@@ -36,7 +34,7 @@ pub mod int_vec_interp {
 
 			}
 
-			
+
 			impl From<BitVec<$n>> for $name {
                             fn from(bv: BitVec<$n>) -> Self {
 				BitVec::[< to_ $name >](bv)
@@ -69,7 +67,6 @@ pub mod int_vec_interp {
     interpretations!(512; u32x16 [u32; 16], u16x32 [u16; 32], i32x16 [i32; 16], i16x32 [i16; 32]);
     interpretations!(64; i64x1 [i64; 1], i32x2 [i32; 2], i16x4 [i16; 4], i8x8 [i8; 8], u64x1 [u64; 1], u32x2 [u32; 2],u16x4 [u16; 4], u8x8 [u8; 8]);
     interpretations!(32; i8x4 [i8; 4], u8x4 [u8; 4]);
-
 }
 use std::convert::*;
 use std::ops::*;

testable-simd-models/src/core_arch/arm_shared/tests/mod.rs

@@ -66,8 +66,8 @@ pub mod conversions {
 
     use super::types;
     use crate::abstractions::bitvec::BitVec;
-    use crate::simd::int_vec_interp::*;
     use crate::abstractions::funarr::FunArray;
+    use crate::simd::int_vec_interp::*;
     macro_rules! convert{
 	($($ty1:ident [$ty2:ty ; $n:literal]),*) => {
 	    $(

testable-simd-models/src/core_arch/x86/models/avx.rs

@@ -14,12 +14,7 @@
 //! [wiki]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
 
 use super::types::*;
-use crate::abstractions::{
-    bit::Bit,
-    bitvec::BitVec,
-    simd::*,
-    simd::int_vec_interp::*
-};
+use crate::abstractions::{bit::Bit, bitvec::BitVec, simd::int_vec_interp::*, simd::*};
 
 mod c_extern {
     use crate::abstractions::simd::int_vec_interp::*;

testable-simd-models/src/core_arch/x86/models/avx2.rs

@@ -19,13 +19,10 @@
 //! [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
 //! [wiki_avx]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
 //! [wiki_fma]: https://en.wikipedia.org/wiki/Fused_multiply-accumulate
-use crate::abstractions::{
-    bitvec::BitVec,
-    simd::int_vec_interp::*
-};
+use crate::abstractions::{bitvec::BitVec, simd::int_vec_interp::*};
 
 mod c_extern {
-    use crate::abstractions::{bit::MachineInteger, simd::*, simd::int_vec_interp::*};
+    use crate::abstractions::{bit::MachineInteger, simd::int_vec_interp::*, simd::*};
     pub fn phaddw(a: i16x16, b: i16x16) -> i16x16 {
         i16x16::from_fn(|i| {
             if i < 4 {

testable-simd-models/src/core_arch/x86/models/sse2.rs

@@ -1,11 +1,6 @@
 //! Streaming SIMD Extensions 2 (SSE2)
 use super::types::*;
-use crate::abstractions::{
-    bit::Bit,
-    bitvec::BitVec,
-    simd::*,
-    simd::int_vec_interp::*
-};
+use crate::abstractions::{bit::Bit, bitvec::BitVec, simd::int_vec_interp::*, simd::*};
 mod c_extern {
     use crate::abstractions::{bit::MachineInteger, simd::int_vec_interp::*};
     pub fn packsswb(a: i16x8, b: i16x8) -> i8x16 {

testable-simd-models/src/core_arch/x86/models/ssse3.rs

@@ -1,10 +1,6 @@
 //! Supplemental Streaming SIMD Extensions 3 (SSSE3)
 
-use crate::abstractions::{
-    bitvec::BitVec,
-    simd::int_vec_interp::*,
-    simd::*,
-};
+use crate::abstractions::{bitvec::BitVec, simd::int_vec_interp::*, simd::*};
 
 use super::types::*;
 

testable-simd-models/src/core_arch/x86/specs/avx.rs

@@ -1,10 +1,6 @@
 use super::types::*;
 
-use crate::abstractions::{
-    bit::Bit,
-    bitvec::BitVec,
-    simd::int_vec_interp::*
-};
+use crate::abstractions::{bit::Bit, bitvec::BitVec, simd::int_vec_interp::*};
 
 pub fn _mm256_set1_epi32(x: i32) -> __m256i {
     i32x8::from_fn(|_| x).into()

testable-simd-models/src/core_arch/x86/specs/avx2.rs

@@ -1,10 +1,6 @@
 use super::types::*;
 
-use crate::abstractions::{
-    bit::Bit,
-    bitvec::BitVec,
-    simd::int_vec_interp::*
-};
+use crate::abstractions::{bit::Bit, bitvec::BitVec, simd::int_vec_interp::*};
 
 pub fn _mm256_mul_epi32(x: __m256i, y: __m256i) -> __m256i {
     let x = BitVec::to_i32x8(x);

testable-simd-models/src/core_arch/x86/specs/sse2.rs

@@ -1,9 +1,6 @@
 use super::types::*;
 
-use crate::abstractions::{
-    bitvec::BitVec,
-    simd::int_vec_interp::*
-};
+use crate::abstractions::{bitvec::BitVec, simd::int_vec_interp::*};
 pub fn _mm_set1_epi16(a: i16) -> __m128i {
     i16x8::from_fn(|_| a).into()
 }