add to prefix ccu typedefs

zelenski · CS107E BOT · commit 67faaa537142 · 2024-11-22T17:52:39.000Z
commit 0ad919e9ebf529c9f221363567b17e51010906b2
Author: Julie Zelenski &lt;zelenski@users.noreply.github.com&gt;
Date:   Fri Nov 22 09:47:48 2024 -0800

    add to prefix ccu typedefs
diff --git a/cs107e/include/ccu.h b/cs107e/include/ccu.h
@@ -10,9 +10,9 @@
 #include <stdint.h>
 
 /*
- * Type: `module_clk_id_t`, `bgr_id_t`, `pll_id_t`
+ * Type: `ccu_module_id_t`, `ccu_bgr_id_t`, `ccu_pll_id_t`
  *
- * Type used to identify a ccu register by id (offset).
+ * Type used to identify a ccu clock register by id (offset).
  * We list only the ids of those ccu registers that we are using.
  */
 
@@ -24,27 +24,29 @@ typedef enum { // ids for Module Clock registers
     CCU_DRAM_CLK_REG        = 0x0800,
     CCU_HDMI_24M_CLK_REG    = 0x0B04,
     CCU_TCONTV_CLK_REG      = 0x0B80,
+    CCU_SPI0_CLK_REG        = 0x0940,
+    CCU_SPI1_CLK_REG        = 0x0944,
     CCU_I2S0_CLK_REG        = 0x0A10,
     CCU_I2S1_CLK_REG        = 0x0A14,
     CCU_I2S2_CLK_REG        = 0x0A18,
-    CCU_SPI0_CLK_REG        = 0x0940,
-    CCU_SPI1_CLK_REG        = 0x0944,
-} module_clk_id_t;
+    CCU_LEDC_CLK_REG        = 0x0BF0,
+} ccu_module_id_t;
 
 typedef enum {  // ids for Bus Gating Reset registers
     CCU_DE_BGR_REG          = 0x060C,  // Display engine
-    CCU_DPSS_TOP_BGR_REG    = 0x0ABC,  // TCON TOP
-    CCU_HDMI_BGR_REG        = 0x0B1C,
-    CCU_TCONTV_BGR_REG      = 0x0B9C,
     CCU_DMA_BGR_REG         = 0x070C,
     CCU_HSTIMER_BGR_REG     = 0x073C,
     CCU_PWM_BGR_REG         = 0x07AC,
     CCU_DRAM_BGR_REG        = 0x080C,
     CCU_UART_BGR_REG        = 0x090C,
-    CCU_I2S_BGR_REG         = 0x0A20,
     CCU_TWI_BGR_REG         = 0x091C,  // TWI == I2C
     CCU_SPI_BGR_REG         = 0x096C,
-} bgr_id_t;
+    CCU_I2S_BGR_REG         = 0x0A20,
+    CCU_DPSS_TOP_BGR_REG    = 0x0ABC,  // TCON TOP
+    CCU_HDMI_BGR_REG        = 0x0B1C,
+    CCU_TCONTV_BGR_REG      = 0x0B9C,
+    CCU_LEDC_BGR_REG        = 0x0BFC,
+} ccu_bgr_id_t;
 
 typedef enum { // ids for PLL registers
     CCU_PLL_CPU_CTRL_REG    = 0x0000,
@@ -55,10 +57,10 @@ typedef enum { // ids for PLL registers
     CCU_PLL_VE_CTRL_REG     = 0x0058,
     CCU_PLL_AUDIO0_CTRL_REG = 0x0078,
     CCU_PLL_AUDIO1_CTRL_REG = 0x0080,
-} pll_id_t;
+} ccu_pll_id_t;
 
 /*
- * Type: `parent_id_t`
+ * Type: `ccu_parent_id_t`
  *
  * Enum type used to identify a clock's parent clock.
  */
@@ -80,7 +82,7 @@ typedef enum {
     PARENT_APB0,
     PARENT_APB1,
     PARENT_PSI,
-} parent_id_t;
+} ccu_parent_id_t;
 
 /*
  * `ccu_config_pll_rate`: Update settings and enable pll
@@ -93,7 +95,7 @@ typedef enum {
  * @param rate     desired rate in hz
  * @return         pll rate of new configuration
  */
-long ccu_config_pll_rate(pll_id_t id, long rate);
+long ccu_config_pll_rate(ccu_pll_id_t id, long rate);
 
 /*
  * `ccu_config_module_clock_rate`: Update settings and enable module clock
@@ -105,7 +107,7 @@ long ccu_config_pll_rate(pll_id_t id, long rate);
  * @param rate      desired rate in hz
  * @return          rate of module clock
  */
-long ccu_config_module_clock_rate(module_clk_id_t id, parent_id_t parent, long rate);
+long ccu_config_module_clock_rate(ccu_module_id_t id, ccu_parent_id_t parent, long rate);
 
 /*
  * `ccu_ungate_bus_clock`: Ungate bus clock
@@ -116,8 +118,8 @@ long ccu_config_module_clock_rate(module_clk_id_t id, parent_id_t parent, long r
  * @param id    id of bgr from bgr enum above
  * @return      rate of bus clock
  */
-long ccu_ungate_bus_clock(bgr_id_t reg_id);
-long ccu_ungate_bus_clock_bits(bgr_id_t reg_id, uint32_t gating_bits, uint32_t reset_bits);
+long ccu_ungate_bus_clock(ccu_bgr_id_t reg_id);
+long ccu_ungate_bus_clock_bits(ccu_bgr_id_t reg_id, uint32_t gating_bits, uint32_t reset_bits);
 
 // for debugging purposes
 void ccu_debug_show_clocks(const char *label);
diff --git a/cs107e/lib/libmango.a b/cs107e/lib/libmango.a
diff --git a/cs107e/src/ccu.c b/cs107e/src/ccu.c
@@ -21,18 +21,18 @@ struct debug_info {
     long (*fn)(uint32_t);
     uint32_t reg_id;
     const char *name;
-    parent_id_t parents[4];
+    ccu_parent_id_t parents[4];
     uint32_t ncount, mcount;
 };
 static struct debug_info *info_for_id(uint32_t id);
-static long debug_rate_pll(pll_id_t id);
-static long debug_rate_clk(module_clk_id_t id);
-static long debug_rate_bgr(bgr_id_t id);
-static long debug_rate_parent(parent_id_t id);
-static int get_parent_src_index(module_clk_id_t id, parent_id_t parent);
-static void validate_pll(pll_id_t id);
-static void validate_module_clk(module_clk_id_t id);
-static void validate_bgr(bgr_id_t id);
+static long debug_rate_pll(ccu_pll_id_t id);
+static long debug_rate_clk(ccu_module_id_t id);
+static long debug_rate_bgr(ccu_bgr_id_t id);
+static long debug_rate_parent(ccu_parent_id_t id);
+static int get_parent_src_index(ccu_module_id_t id, ccu_parent_id_t parent);
+static void validate_pll(ccu_pll_id_t id);
+static void validate_module_clk(ccu_module_id_t id);
+static void validate_bgr(ccu_bgr_id_t id);
 
 typedef union {
     struct {
@@ -88,7 +88,7 @@ static volatile uint32_t *reg_for_id(uint32_t raw_offset) {
 // commonly used PLL rates and list in this table for easy access.
 // if you need an additional rate config, simply add to this table
 static const struct pll_config_t {
-    pll_id_t pll_id;
+    ccu_pll_id_t pll_id;
     uint32_t rate;
     struct { uint8_t P; uint8_t N; uint8_t M1; uint8_t M0; };
 } pll_table[] = {
@@ -99,7 +99,7 @@ static const struct pll_config_t {
     {0}
 };
 
-static const struct pll_config_t *get_pll_config_for_rate(pll_id_t id, long rate) {
+static const struct pll_config_t *get_pll_config_for_rate(ccu_pll_id_t id, long rate) {
     for (const struct pll_config_t *cfg = pll_table; cfg->rate != 0; cfg++) {
         if (cfg->pll_id == id && cfg->rate == rate) return cfg;
     }
@@ -110,7 +110,7 @@ static const struct pll_config_t *get_pll_config_for_rate(pll_id_t id, long rate
 #define BITS_N_M1(n, m1)             ((pll_reg_t){ .factor_n=n, .factor_m1=m1 }).bits
 #define BITS_P_N_M1_M0(p, n, m1, m0) ((pll_reg_t){ .factor_p=p, .factor_n=n, .factor_m1=m1, .factor_m0=m0 }).bits;
 
-static void get_pll_bits(pll_id_t id, long rate, uint32_t *factor_mask, uint32_t *new_factors) {
+static void get_pll_bits(ccu_pll_id_t id, long rate, uint32_t *factor_mask, uint32_t *new_factors) {
     uint32_t out_mhz;
     const struct pll_config_t *cfg = get_pll_config_for_rate(id, rate);
     if (!cfg) error("No matching pll config found in rate table.");
@@ -170,7 +170,7 @@ static void update_pll_bits(volatile uint32_t *reg, uint32_t factor_mask, uint32
     *reg |= OUT_ENA;            // re-enable output
 }
 
-long ccu_config_pll_rate(pll_id_t id, long rate) {
+long ccu_config_pll_rate(ccu_pll_id_t id, long rate) {
     validate_pll(id);
     uint32_t factor_mask, new_factors;
     get_pll_bits(id, rate, &factor_mask, &new_factors);
@@ -180,7 +180,7 @@ long ccu_config_pll_rate(pll_id_t id, long rate) {
     return set_rate;
 }
 
-static uint32_t get_module_clk_bits(module_clk_id_t id, parent_id_t parent, long rate) {
+static uint32_t get_module_clk_bits(ccu_module_id_t id, ccu_parent_id_t parent, long rate) {
     int src = get_parent_src_index(id, parent);
     if (src == -1) error("Parent id is not valid for module clock")
     long parent_rate = debug_rate_parent(parent);
@@ -220,7 +220,7 @@ static void update_clock_bits(volatile uint32_t *reg, uint32_t bits) {
     *reg |= ENA;    // re-enable
 }
 
-long ccu_config_module_clock_rate(module_clk_id_t id, parent_id_t parent, long rate) {
+long ccu_config_module_clock_rate(ccu_module_id_t id, ccu_parent_id_t parent, long rate) {
     validate_module_clk(id);
     uint32_t new_bits = get_module_clk_bits(id, parent, rate);
     update_clock_bits(reg_for_id(id), new_bits);
@@ -235,7 +235,7 @@ long ccu_config_module_clock_rate(module_clk_id_t id, parent_id_t parent, long r
  *  and then the clock gating bit is enabled to avoid potential problems
  *  caused by the asynchronous release of the reset signal.
  */
-long ccu_ungate_bus_clock_bits(bgr_id_t id, uint32_t gating_bits, uint32_t reset_bits) {
+long ccu_ungate_bus_clock_bits(ccu_bgr_id_t id, uint32_t gating_bits, uint32_t reset_bits) {
     validate_bgr(id);
     volatile uint32_t *reg = reg_for_id(id);
     *reg |= reset_bits;      // de-assert reset
@@ -245,7 +245,7 @@ long ccu_ungate_bus_clock_bits(bgr_id_t id, uint32_t gating_bits, uint32_t reset
 
 // most bus clocks use standard bits for reset/gate
 // general function above allow other use cases
-long ccu_ungate_bus_clock(bgr_id_t id) {
+long ccu_ungate_bus_clock(ccu_bgr_id_t id) {
     const uint32_t standard_gating_bits = 1 << 0;
     const uint32_t standard_reset_bits  = 1 << 16;
     return ccu_ungate_bus_clock_bits(id, standard_gating_bits, standard_reset_bits);
@@ -283,6 +283,7 @@ static struct debug_info info_table[] = {
     { INFO_CLK(CCU_SPI0_CLK_REG),     {PARENT_HOSC, PARENT_PERI, PARENT_PERI_2X}, .ncount=2,.mcount=4 },
     { INFO_CLK(CCU_SPI1_CLK_REG),     {PARENT_HOSC, PARENT_PERI, PARENT_PERI_2X}, .ncount=2,.mcount=4 },
     { INFO_CLK(CCU_I2S2_CLK_REG),     {PARENT_AUDIO0, NOT_IN_MODEL, NOT_IN_MODEL, PARENT_AUDIO1_DIV5}, .ncount=0,.mcount=5},
+    { INFO_CLK(CCU_LEDC_CLK_REG),     {PARENT_HOSC, PARENT_PERI, NOT_IN_MODEL, NOT_IN_MODEL}, .ncount=2,.mcount=4},
     { .name= "Bus Clock" },
     { INFO_BGR(CCU_DE_BGR_REG),       {PARENT_AHB0} },
     { INFO_BGR(CCU_DPSS_TOP_BGR_REG), {PARENT_AHB0} },
@@ -295,10 +296,11 @@ static struct debug_info info_table[] = {
     { INFO_BGR(CCU_I2S_BGR_REG),      {PARENT_APB0} },
     { INFO_BGR(CCU_TWI_BGR_REG),      {PARENT_APB1} },
     { INFO_BGR(CCU_SPI_BGR_REG),      {PARENT_APB1} },
+    { INFO_BGR(CCU_LEDC_BGR_REG),     {PARENT_APB1} },
     {0},
   };
 
-static int get_parent_src_index(module_clk_id_t id, parent_id_t parent) {
+static int get_parent_src_index(ccu_module_id_t id, ccu_parent_id_t parent) {
     for (struct debug_info *info = info_table; info->name; info++) {
         if (info->reg_id == id) {
             for (int i = 0; i < sizeof(info->parents)/sizeof(*info->parents); i++) {
@@ -330,7 +332,7 @@ void ccu_debug_show_clocks(const char *label) {
     }
 }
 
-static long debug_rate_parent(parent_id_t id) {
+static long debug_rate_parent(ccu_parent_id_t id) {
     int mult = 1, div = 1;
     switch (id) {
         case NOT_IN_MODEL:      return -1;
@@ -354,7 +356,7 @@ static long debug_rate_parent(parent_id_t id) {
     return -1;
 }
 
-static long debug_rate_pll(pll_id_t id) {
+static long debug_rate_pll(ccu_pll_id_t id) {
     pll_reg_t pll;
     pll.bits = *reg_for_id(id);
     if (!pll.ena || !pll.output_ena) return 0;
@@ -373,34 +375,34 @@ static long debug_rate_pll(pll_id_t id) {
     }
 }
 
-static long debug_rate_clk(module_clk_id_t id) {
+static long debug_rate_clk(ccu_module_id_t id) {
     module_clk_reg_t clk;
     clk.bits = *reg_for_id(id);
     if (id > CCU_APB1_CLK_REG && !clk.ena) return 0; // cheezy (ena bits not applicable for psi/apb?)
     int n = 1 << clk.factor_n;
     int m = clk.factor_m + 1;
     struct debug_info *i = info_for_id(id);
-    parent_id_t parent = i->parents[clk.src];
+    ccu_parent_id_t parent = i->parents[clk.src];
     return debug_rate_parent(parent)/n/m;
 }
 
-static long debug_rate_bgr(bgr_id_t id) {
+static long debug_rate_bgr(ccu_bgr_id_t id) {
     uint32_t val = *reg_for_id(id);
     struct debug_info *i = info_for_id(id);
     return (val & 0xff) ? debug_rate_parent(i->parents[0]) : 0;
 }
 
-static void validate_pll(pll_id_t id) {
+static void validate_pll(ccu_pll_id_t id) {
     struct debug_info *info = info_for_id(id);
     if (!info || info->fn != debug_rate_pll) error("PLL id is not valid");
 }
 
-static void validate_module_clk(module_clk_id_t id) {
+static void validate_module_clk(ccu_module_id_t id) {
     struct debug_info *info = info_for_id(id);
     if (!info || info->fn != debug_rate_clk) error("Module clock id is not valid");
 }
 
-static void validate_bgr(bgr_id_t id) {
+static void validate_bgr(ccu_bgr_id_t id) {
     struct debug_info *info = info_for_id(id);
     if (!info || info->fn != debug_rate_bgr) error("Bus clock id is not valid");
 }
diff --git a/cs107e/src/hdmi.c b/cs107e/src/hdmi.c
@@ -77,11 +77,11 @@ struct display_timing {
     } horiz, vert;
     struct {
         long rate;
-        pll_id_t id;
+        ccu_pll_id_t id;
     } pll;
     struct {
         long rate;
-        parent_id_t parent;
+        ccu_parent_id_t parent;
     } tcon_clk, de_clk;     // TCONTV and DE clocks
 };
 
