updated intro lecture release

commit cbee0462eaad314cd3353b9d2b2e186f4114a1a7
Author: Chris Gregg <[email protected]>
Date:   Mon Jan 6 09:06:52 2025 -0800

    updated intro lecture release

Author: tofergregg

_data/unreleased.csv

@@ -35,7 +35,6 @@ permalink,title,released
 "/lectures/OOP/","Object-oriented programming",false
 "/lectures/Output/","Output",false
 "/lectures/Project/","Project",false
-"/lectures/RISC-V/","RISC-V architecture",false
 "/lectures/Sensors/","Sensor Input",false
 "/lectures/Serial/","Communication and the Serial Protocol",false
 "/lectures/Wrap/","Wrap or There and Back Again",false

lectures/RISC-V/README.md

@@ -0,0 +1,9 @@
+---
+released: true
+permalink: /lectures/RISC-V/
+title: "RISC-V architecture"
+readings: |
+    + Here is a link to the [Ripes simulator](https://ripes.me/) demoed in lecture.
+    + Our [one-page guide to RISC-V](/guides/riscv-onepage).
+    + (Not light reading, but the real deal on the design of RISC-V) Andrew Waterman's PhD Thesis, "Design of the RISC-V Instruction Set Architecuture" <https://people.eecs.berkeley.edu/~krste/papers/EECS-2016-1.pdf>
+---

lectures/RISC-V/code/Makefile

@@ -0,0 +1,24 @@
+all: list
+
+OBJDUMP_FLAGS = -d
+
+%.riscv.o: %.c
+	riscv64-unknown-elf-gcc -O2 -march=rv64im -mabi=lp64 -c $< -o $@
+
+%.intel.o: %.c
+	clang -O2 -fomit-frame-pointer -c $< -o $@
+
+%.arm.o: %.c
+	arm-none-eabi-gcc -O2 -c $< -o $@
+
+# Extra recipe to disassemble the compiled program
+list: code.riscv.o code.intel.o code.arm.o
+	arm-none-eabi-objdump $(OBJDUMP_FLAGS) -d code.arm.o >arm.list
+	riscv64-unknown-elf-objdump $(OBJDUMP_FLAGS) -d code.riscv.o >riscv.list
+	otool -v -t -j code.intel.o >intel.list
+
+clean:
+	rm -rf *.o *.bin *.elf *.list *~ code
+
+.PHONY: all clean run list
+.PRECIOUS:  %.elf

lectures/RISC-V/code/arm.list

@@ -0,0 +1,27 @@
+
+code.arm.o:     file format elf32-littlearm
+
+
+Disassembly of section .text:
+
+00000000 <set>:
+   0:	e7802101 	str	r2, [r0, r1, lsl #2]
+   4:	e12fff1e 	bx	lr
+
+00000008 <eitheror>:
+   8:	e3110001 	tst	r1, #1, 0
+   c:	13a01000 	movne	r1, #0, 0
+  10:	e5801020 	str	r1, [r0, #32]
+  14:	e12fff1e 	bx	lr
+
+00000018 <count_bits>:
+  18:	e2503000 	subs	r3, r0, #0, 0
+  1c:	0a000005 	beq	38 <count_bits+0x20>
+  20:	e3a00000 	mov	r0, #0, 0
+  24:	e3130001 	tst	r3, #1, 0
+  28:	12800001 	addne	r0, r0, #1, 0
+  2c:	e1b030a3 	lsrs	r3, r3, #1
+  30:	1afffffb 	bne	24 <count_bits+0xc>
+  34:	e12fff1e 	bx	lr
+  38:	e1a00003 	mov	r0, r3
+  3c:	e12fff1e 	bx	lr

lectures/RISC-V/code/code.c

@@ -0,0 +1,21 @@
+
+void set(int arr[], unsigned long index, int val) {
+   arr[index] = val;
+}
+
+void eitheror(int arr[], int val) {
+    if (val % 2 == 0) {
+        arr[8] = val;
+    } else {
+        arr[8] = 0;
+    }
+}
+
+int count_bits(unsigned int val) {
+    int count = 0;
+    while (val != 0) {
+        if (val & 1) count++;
+        val >>= 1;
+    }
+    return count;
+}

lectures/RISC-V/code/intel.list

@@ -0,0 +1,27 @@
+code.intel.o:
+(__TEXT,__text) section
+_set:
+0000000000000000	8914b7          	movl	%edx, (%rdi,%rsi,4)
+0000000000000003	c3              	retq
+0000000000000004	6666662e0f1f840000000000	nopw	%cs:(%rax,%rax)
+_eitheror:
+0000000000000010	31c0            	xorl	%eax, %eax
+0000000000000012	40f6c601        	testb	$0x1, %sil
+0000000000000016	0f44c6          	cmovel	%esi, %eax
+0000000000000019	894720          	movl	%eax, 0x20(%rdi)
+000000000000001c	c3              	retq
+000000000000001d	0f1f00          	nopl	(%rax)
+_count_bits:
+0000000000000020	31c0            	xorl	%eax, %eax
+0000000000000022	85ff            	testl	%edi, %edi
+0000000000000024	741a            	je	0x40
+0000000000000026	89f9            	movl	%edi, %ecx
+0000000000000028	0f1f840000000000	nopl	(%rax,%rax)
+0000000000000030	89fa            	movl	%edi, %edx
+0000000000000032	83e201          	andl	$0x1, %edx
+0000000000000035	01d0            	addl	%edx, %eax
+0000000000000037	d1e9            	shrl	%ecx
+0000000000000039	83ff01          	cmpl	$0x1, %edi
+000000000000003c	89cf            	movl	%ecx, %edi
+000000000000003e	77f0            	ja	0x30
+0000000000000040	c3              	retq

lectures/RISC-V/code/riscv.list

@@ -0,0 +1,36 @@
+
+code.riscv.o:     file format elf64-littleriscv
+
+
+Disassembly of section .text:
+
+0000000000000000 <set>:
+   0:	00259593          	sll	a1,a1,0x2
+   4:	00b50533          	add	a0,a0,a1
+   8:	00c52023          	sw	a2,0(a0)
+   c:	00008067          	ret
+
+0000000000000010 <eitheror>:
+  10:	0015f793          	and	a5,a1,1
+  14:	fff78793          	add	a5,a5,-1
+  18:	00f5f5b3          	and	a1,a1,a5
+  1c:	02b52023          	sw	a1,32(a0)
+  20:	00008067          	ret
+
+0000000000000024 <count_bits>:
+  24:	00050793          	mv	a5,a0
+  28:	00000513          	li	a0,0
+  2c:	00078e63          	beqz	a5,48 <.L10>
+
+0000000000000030 <.L9>:
+  30:	0017f713          	and	a4,a5,1
+  34:	0017d79b          	srlw	a5,a5,0x1
+  38:	00070463          	beqz	a4,40 <.L8>
+  3c:	0015051b          	addw	a0,a0,1
+
+0000000000000040 <.L8>:
+  40:	fe0798e3          	bnez	a5,30 <.L9>
+  44:	00008067          	ret
+
+0000000000000048 <.L10>:
+  48:	00008067          	ret