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bebarinobebarino
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Merge tag 'v6.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner: - Export more clocks for Rockchip rk3128 peripherals - Convert Rockchip clk drivers to use kmemdup_array() - Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers * tag 'v6.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: clock: rk3188-cru-common: remove CLK_NR_CLKS clk: rockchip: rk3188: Drop CLK_NR_CLKS usage clk: rockchip: Switch to use kmemdup_array() clk: rockchip: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Drop CLK_NR_CLKS clk: rockchip: rk3128: Drop CLK_NR_CLKS usage clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks clk: rockchip: rk3128: Export PCLK_MIPIPHY dt-bindings: clock: rk3128: Add PCLK_MIPIPHY
2 parents 1613e60 + d89e809 commit 04718d1

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6 files changed

+41
-20
lines changed

6 files changed

+41
-20
lines changed

‎drivers/clk/rockchip/clk-cpu.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -369,9 +369,8 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
369369

370370
if (nrates > 0) {
371371
cpuclk->rate_count = nrates;
372-
cpuclk->rate_table = kmemdup(rates,
373-
sizeof(*rates) * nrates,
374-
GFP_KERNEL);
372+
cpuclk->rate_table = kmemdup_array(rates, nrates, sizeof(*rates),
373+
GFP_KERNEL);
375374
if (!cpuclk->rate_table) {
376375
ret = -ENOMEM;
377376
goto unregister_notifier;

‎drivers/clk/rockchip/clk-pll.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1136,10 +1136,10 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
11361136
len++;
11371137

11381138
pll->rate_count = len;
1139-
pll->rate_table = kmemdup(rate_table,
1140-
pll->rate_count *
1141-
sizeof(struct rockchip_pll_rate_table),
1142-
GFP_KERNEL);
1139+
pll->rate_table = kmemdup_array(rate_table,
1140+
pll->rate_count,
1141+
sizeof(*pll->rate_table),
1142+
GFP_KERNEL);
11431143
WARN(!pll->rate_table,
11441144
"%s: could not allocate rate table for %s\n",
11451145
__func__, name);

‎drivers/clk/rockchip/clk-rk3128.c‎

Lines changed: 19 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -526,7 +526,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
526526
GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
527527
GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS),
528528
GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
529-
GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS),
529+
GATE(PCLK_MIPIPHY, "pclk_mipiphy", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
530530

531531
GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
532532
GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),
@@ -553,6 +553,7 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
553553
RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
554554
RK2928_CLKGATE_CON(3), 15, GFLAGS),
555555

556+
GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
556557
GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
557558
GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
558559
};
@@ -563,23 +564,28 @@ static const char *const rk3128_critical_clocks[] __initconst = {
563564
"pclk_cpu",
564565
"aclk_peri",
565566
"hclk_peri",
567+
"hclk_vio_h2p",
566568
"pclk_peri",
567569
"pclk_pmu",
568570
"sclk_timer5",
569571
};
570572

571-
static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
573+
static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np,
574+
unsigned long soc_nr_clks)
572575
{
573576
struct rockchip_clk_provider *ctx;
577+
unsigned long common_nr_clks;
574578
void __iomem *reg_base;
575579

580+
common_nr_clks = rockchip_clk_find_max_clk_id(common_clk_branches,
581+
ARRAY_SIZE(common_clk_branches)) + 1;
576582
reg_base = of_iomap(np, 0);
577583
if (!reg_base) {
578584
pr_err("%s: could not map cru region\n", __func__);
579585
return ERR_PTR(-ENOMEM);
580586
}
581587

582-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
588+
ctx = rockchip_clk_init(np, reg_base, max(common_nr_clks, soc_nr_clks));
583589
if (IS_ERR(ctx)) {
584590
pr_err("%s: rockchip clk init failed\n", __func__);
585591
iounmap(reg_base);
@@ -608,8 +614,12 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device
608614
static void __init rk3126_clk_init(struct device_node *np)
609615
{
610616
struct rockchip_clk_provider *ctx;
617+
unsigned long soc_nr_clks;
611618

612-
ctx = rk3128_common_clk_init(np);
619+
soc_nr_clks = rockchip_clk_find_max_clk_id(rk3126_clk_branches,
620+
ARRAY_SIZE(rk3126_clk_branches)) + 1;
621+
622+
ctx = rk3128_common_clk_init(np, soc_nr_clks);
613623
if (IS_ERR(ctx))
614624
return;
615625

@@ -626,8 +636,12 @@ CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
626636
static void __init rk3128_clk_init(struct device_node *np)
627637
{
628638
struct rockchip_clk_provider *ctx;
639+
unsigned long soc_nr_clks;
640+
641+
soc_nr_clks = rockchip_clk_find_max_clk_id(rk3128_clk_branches,
642+
ARRAY_SIZE(rk3128_clk_branches)) + 1;
629643

630-
ctx = rk3128_common_clk_init(np);
644+
ctx = rk3128_common_clk_init(np, soc_nr_clks);
631645
if (IS_ERR(ctx))
632646
return;
633647

‎drivers/clk/rockchip/clk-rk3188.c‎

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -757,9 +757,11 @@ static const char *const rk3188_critical_clocks[] __initconst = {
757757
"sclk_mac_lbtest",
758758
};
759759

760-
static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
760+
static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np,
761+
unsigned long soc_nr_clks)
761762
{
762763
struct rockchip_clk_provider *ctx;
764+
unsigned long common_nr_clks;
763765
void __iomem *reg_base;
764766

765767
reg_base = of_iomap(np, 0);
@@ -768,7 +770,9 @@ static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device
768770
return ERR_PTR(-ENOMEM);
769771
}
770772

771-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
773+
common_nr_clks = rockchip_clk_find_max_clk_id(common_clk_branches,
774+
ARRAY_SIZE(common_clk_branches)) + 1;
775+
ctx = rockchip_clk_init(np, reg_base, max(common_nr_clks, soc_nr_clks));
772776
if (IS_ERR(ctx)) {
773777
pr_err("%s: rockchip clk init failed\n", __func__);
774778
iounmap(reg_base);
@@ -789,8 +793,11 @@ static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device
789793
static void __init rk3066a_clk_init(struct device_node *np)
790794
{
791795
struct rockchip_clk_provider *ctx;
796+
unsigned long soc_nr_clks;
792797

793-
ctx = rk3188_common_clk_init(np);
798+
soc_nr_clks = rockchip_clk_find_max_clk_id(rk3066a_clk_branches,
799+
ARRAY_SIZE(rk3066a_clk_branches)) + 1;
800+
ctx = rk3188_common_clk_init(np, soc_nr_clks);
794801
if (IS_ERR(ctx))
795802
return;
796803

@@ -812,11 +819,14 @@ CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
812819
static void __init rk3188a_clk_init(struct device_node *np)
813820
{
814821
struct rockchip_clk_provider *ctx;
822+
unsigned long soc_nr_clks;
815823
struct clk *clk1, *clk2;
816824
unsigned long rate;
817825
int ret;
818826

819-
ctx = rk3188_common_clk_init(np);
827+
soc_nr_clks = rockchip_clk_find_max_clk_id(rk3188_clk_branches,
828+
ARRAY_SIZE(rk3188_clk_branches)) + 1;
829+
ctx = rk3188_common_clk_init(np, soc_nr_clks);
820830
if (IS_ERR(ctx))
821831
return;
822832

‎include/dt-bindings/clock/rk3128-cru.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,7 @@
116116
#define PCLK_GMAC 367
117117
#define PCLK_PMU_PRE 368
118118
#define PCLK_SIM_CARD 369
119+
#define PCLK_MIPIPHY 370
119120

120121
/* hclk gates */
121122
#define HCLK_SPDIF 440
@@ -143,8 +144,7 @@
143144
#define HCLK_TSP 475
144145
#define HCLK_CRYPTO 476
145146
#define HCLK_PERI 478
146-
147-
#define CLK_NR_CLKS (HCLK_PERI + 1)
147+
#define HCLK_SFC 479
148148

149149
/* soft-reset indices */
150150
#define SRST_CORE0_PO 0

‎include/dt-bindings/clock/rk3188-cru-common.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -132,8 +132,6 @@
132132
#define HCLK_VDPU 472
133133
#define HCLK_HDMI 473
134134

135-
#define CLK_NR_CLKS (HCLK_HDMI + 1)
136-
137135
/* soft-reset indices */
138136
#define SRST_MCORE 2
139137
#define SRST_CORE0 3

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