clk: sophgo: avoid open-coded 64-bit division

On 32-bit architectures, the 64-bit division leads to a link failure:

arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate':
clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod'

This one is not called in a fast path, and there is already another div_u64()
variant used in the same function, so convert it to div64_u64_rem().

Fixes: 80fd61e ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Reviewed-by: Inochi Amaoto <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

Author: arndb

drivers/clk/sophgo/clk-cv18xx-pll.c

@@ -205,8 +205,7 @@ static unsigned long fpll_calc_rate(unsigned long parent_rate,
 	unsigned long rate;
 
 	dividend <<= PLL_SYN_FACTOR_DOT_POS - 1;
-	rate = dividend / factor;
-	dividend %= factor;
+	rate = div64_u64_rem(dividend, factor, &dividend);
 
 	if (is_full_parent) {
 		dividend <<= 1;