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Cruise Hungalexdeucher
Cruise Hung
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alexdeucher
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drm/amd/display: Support external tunneling feature
[Why & How] The original code only supports the tunneling for embedded one. To support external tunneling feature, it needs to check Tunneling_Support bit register. Reviewed-by: Wenjing Liu <[email protected]> Reviewed-by: Jun Lei <[email protected]> Signed-off-by: Cruise Hung <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
1 parent fe1903b commit 17accf4

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14 files changed

+126
-80
lines changed

14 files changed

+126
-80
lines changed

‎drivers/gpu/drm/amd/display/dc/core/dc_resource.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3911,6 +3911,10 @@ enum dc_status resource_map_pool_resources(
39113911
if (!dc->link_srv->dp_decide_link_settings(stream,
39123912
&pipe_ctx->link_config.dp_link_settings))
39133913
return DC_FAIL_DP_LINK_BANDWIDTH;
3914+
3915+
dc->link_srv->dp_decide_tunnel_settings(stream,
3916+
&pipe_ctx->link_config.dp_tunnel_settings);
3917+
39143918
if (dc->link_srv->dp_get_encoding_format(
39153919
&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
39163920
pipe_ctx->stream_res.hpo_dp_stream_enc =

‎drivers/gpu/drm/amd/display/dc/dc_dp_types.h‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,11 @@ struct dc_link_settings {
159159
uint8_t link_rate_set;
160160
};
161161

162+
struct dc_tunnel_settings {
163+
bool should_enable_dp_tunneling;
164+
bool should_use_dp_bw_allocation;
165+
};
166+
162167
union dc_dp_ffe_preset {
163168
struct {
164169
uint8_t level : 4;
@@ -943,10 +948,20 @@ union dpia_info {
943948
uint8_t raw;
944949
};
945950

951+
/* DPCD[0xE0020] USB4_DRIVER_BW_CAPABILITY register. */
952+
union usb4_driver_bw_cap {
953+
struct {
954+
uint8_t rsvd :7;
955+
uint8_t driver_bw_alloc_support :1;
956+
} bits;
957+
uint8_t raw;
958+
};
959+
946960
/* DP Tunneling over USB4 */
947961
struct dpcd_usb4_dp_tunneling_info {
948962
union dp_tun_cap_support dp_tun_cap;
949963
union dpia_info dpia_info;
964+
union usb4_driver_bw_cap driver_bw_cap;
950965
uint8_t usb4_driver_id;
951966
uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
952967
};
@@ -1486,5 +1501,11 @@ struct dp_trace {
14861501
# ifndef DP_TUNNELING_BW_ALLOC_CAP_CHANGED
14871502
# define DP_TUNNELING_BW_ALLOC_CAP_CHANGED (1 << 3)
14881503
# endif
1504+
# ifndef DPTX_BW_ALLOC_UNMASK_IRQ
1505+
# define DPTX_BW_ALLOC_UNMASK_IRQ (1 << 6)
1506+
# endif
1507+
# ifndef DPTX_BW_ALLOC_MODE_ENABLE
1508+
# define DPTX_BW_ALLOC_MODE_ENABLE (1 << 7)
1509+
# endif
14891510

14901511
#endif /* DC_DP_TYPES_H */

‎drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1550,7 +1550,7 @@ static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)
15501550
struct dc_link_settings *link_settings = &pipe_ctx->link_config.dp_link_settings;
15511551
const struct dc *dc = pipe_ctx->stream->link->dc;
15521552

1553-
if (pipe_ctx->stream->link->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
1553+
if (pipe_ctx->link_config.dp_tunnel_settings.should_enable_dp_tunneling == false)
15541554
return false;
15551555

15561556
// Not necessary for MST configurations

‎drivers/gpu/drm/amd/display/dc/inc/core_types.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -384,7 +384,9 @@ struct link_resource {
384384

385385
struct link_config {
386386
struct dc_link_settings dp_link_settings;
387+
struct dc_tunnel_settings dp_tunnel_settings;
387388
};
389+
388390
union pipe_update_flags {
389391
struct {
390392
uint32_t enable : 1;

‎drivers/gpu/drm/amd/display/dc/inc/link.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,9 @@ struct link_service {
207207
bool (*dp_decide_link_settings)(
208208
struct dc_stream_state *stream,
209209
struct dc_link_settings *link_setting);
210+
void (*dp_decide_tunnel_settings)(
211+
struct dc_stream_state *stream,
212+
struct dc_tunnel_settings *dp_tunnel_setting);
210213
enum dp_link_encoding (*mst_decide_link_encoding_format)(
211214
const struct dc_link *link);
212215
bool (*edp_decide_link_settings)(struct dc_link *link,

‎drivers/gpu/drm/amd/display/dc/link/link_detection.c‎

Lines changed: 6 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -611,6 +611,7 @@ static bool detect_dp(struct dc_link *link,
611611
link->dpcd_caps.dongle_type = sink_caps->dongle_type;
612612
link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
613613
link->dpcd_caps.dpcd_rev.raw = 0;
614+
link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0;
614615
}
615616

616617
return true;
@@ -1007,21 +1008,11 @@ static bool detect_link_and_local_sink(struct dc_link *link,
10071008
link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
10081009
link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
10091010

1010-
/*
1011-
* If this is DP over USB4 link then we need to:
1012-
* - Enable BW ALLOC support on DPtx if applicable
1013-
*/
1014-
if (dc->config.usb4_bw_alloc_support) {
1015-
if (link_dp_dpia_set_dptx_usb4_bw_alloc_support(link)) {
1016-
/* update with non reduced link cap if bw allocation mode is supported */
1017-
if (link->dpia_bw_alloc_config.nrd_max_link_rate &&
1018-
link->dpia_bw_alloc_config.nrd_max_lane_count) {
1019-
link->reported_link_cap.link_rate =
1020-
link->dpia_bw_alloc_config.nrd_max_link_rate;
1021-
link->reported_link_cap.lane_count =
1022-
link->dpia_bw_alloc_config.nrd_max_lane_count;
1023-
}
1024-
}
1011+
if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
1012+
&& link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
1013+
&& link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) {
1014+
if (link_dpia_enable_usb4_dp_bw_alloc_mode(link) == false)
1015+
link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false;
10251016
}
10261017
break;
10271018
}

‎drivers/gpu/drm/amd/display/dc/link/link_dpms.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2374,7 +2374,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
23742374
update_psp_stream_config(pipe_ctx, true);
23752375
dc->hwss.blank_stream(pipe_ctx);
23762376

2377-
if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
2377+
if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)
23782378
deallocate_usb4_bandwidth(pipe_ctx->stream);
23792379

23802380
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
@@ -2442,7 +2442,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
24422442
if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) {
24432443
/* reset internal save state to default since eDP is off */
24442444
enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link);
2445-
/* since current psp not loaded, we need to reset it to default*/
2445+
/* since current psp not loaded, we need to reset it to default */
24462446
link->panel_mode = panel_mode;
24472447
}
24482448
}
@@ -2620,7 +2620,7 @@ void link_set_dpms_on(
26202620
if (dc_is_dp_signal(pipe_ctx->stream->signal))
26212621
dp_set_hblank_reduction_on_rx(pipe_ctx);
26222622

2623-
if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
2623+
if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)
26242624
allocate_usb4_bandwidth(pipe_ctx->stream);
26252625

26262626
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

‎drivers/gpu/drm/amd/display/dc/link/link_factory.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ static void construct_link_service_dp_capability(struct link_service *link_srv)
156156
link_srv->dp_get_encoding_format = link_dp_get_encoding_format;
157157
link_srv->dp_should_enable_fec = dp_should_enable_fec;
158158
link_srv->dp_decide_link_settings = link_decide_link_settings;
159+
link_srv->dp_decide_tunnel_settings = link_decide_dp_tunnel_settings;
159160
link_srv->mst_decide_link_encoding_format =
160161
mst_decide_link_encoding_format;
161162
link_srv->edp_decide_link_settings = edp_decide_link_settings;

‎drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2021,11 +2021,9 @@ static bool retrieve_link_cap(struct dc_link *link)
20212021
sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw));
20222022

20232023
/* Read DP tunneling information. */
2024-
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
2025-
status = dpcd_get_tunneling_device_data(link);
2026-
if (status != DC_OK)
2027-
dm_error("%s: Read DP tunneling device data failed.\n", __func__);
2028-
}
2024+
status = dpcd_get_tunneling_device_data(link);
2025+
if (status != DC_OK)
2026+
dm_error("%s: Read DP tunneling device data failed.\n", __func__);
20292027

20302028
retrieve_cable_id(link);
20312029
dpcd_write_cable_id_to_dprx(link);

‎drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c‎

Lines changed: 47 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,36 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)
6262
if (status != DC_OK)
6363
goto err;
6464

65+
link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw =
66+
dpcd_dp_tun_data[DP_TUNNELING_CAPABILITIES_SUPPORT - DP_TUNNELING_CAPABILITIES_SUPPORT];
67+
68+
if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling == false)
69+
goto err;
70+
71+
link->dpcd_caps.usb4_dp_tun_info.dpia_info.raw =
72+
dpcd_dp_tun_data[DP_IN_ADAPTER_INFO - DP_TUNNELING_CAPABILITIES_SUPPORT];
73+
link->dpcd_caps.usb4_dp_tun_info.usb4_driver_id =
74+
dpcd_dp_tun_data[DP_USB4_DRIVER_ID - DP_TUNNELING_CAPABILITIES_SUPPORT];
75+
76+
if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc) {
77+
status = core_link_read_dpcd(link, USB4_DRIVER_BW_CAPABILITY,
78+
dpcd_dp_tun_data, 1);
79+
80+
if (status != DC_OK)
81+
goto err;
82+
83+
link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.raw = dpcd_dp_tun_data[0];
84+
}
85+
86+
DC_LOG_DEBUG("%s: Link[%d] DP tunneling support (RouterId=%d AdapterId=%d) "
87+
"DPIA_BW_Alloc_support=%d "
88+
"CM_BW_Alloc_support=%d ",
89+
__func__, link->link_index,
90+
link->dpcd_caps.usb4_dp_tun_info.usb4_driver_id,
91+
link->dpcd_caps.usb4_dp_tun_info.dpia_info.bits.dpia_num,
92+
link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc,
93+
link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);
94+
6595
status = core_link_read_dpcd(
6696
link,
6797
DP_USB4_ROUTER_TOPOLOGY_ID,
@@ -71,13 +101,6 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)
71101
if (status != DC_OK)
72102
goto err;
73103

74-
link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw =
75-
dpcd_dp_tun_data[DP_TUNNELING_CAPABILITIES_SUPPORT - DP_TUNNELING_CAPABILITIES_SUPPORT];
76-
link->dpcd_caps.usb4_dp_tun_info.dpia_info.raw =
77-
dpcd_dp_tun_data[DP_IN_ADAPTER_INFO - DP_TUNNELING_CAPABILITIES_SUPPORT];
78-
link->dpcd_caps.usb4_dp_tun_info.usb4_driver_id =
79-
dpcd_dp_tun_data[DP_USB4_DRIVER_ID - DP_TUNNELING_CAPABILITIES_SUPPORT];
80-
81104
for (i = 0; i < DPCD_USB4_TOPOLOGY_ID_LEN; i++)
82105
link->dpcd_caps.usb4_dp_tun_info.usb4_topology_id[i] = dpcd_topology_data[i];
83106

@@ -120,3 +143,20 @@ bool dpia_query_hpd_status(struct dc_link *link)
120143
return link->hpd_status;
121144
}
122145

146+
void link_decide_dp_tunnel_settings(struct dc_stream_state *stream,
147+
struct dc_tunnel_settings *dp_tunnel_setting)
148+
{
149+
struct dc_link *link = stream->link;
150+
151+
memset(dp_tunnel_setting, 0, sizeof(*dp_tunnel_setting));
152+
153+
if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT) || (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
154+
dp_tunnel_setting->should_enable_dp_tunneling =
155+
link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling;
156+
157+
if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
158+
&& link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support)
159+
dp_tunnel_setting->should_use_dp_bw_allocation = true;
160+
}
161+
}
162+

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