|
30 | 30 |
|
31 | 31 | /* Driver-specific board quirks: from bit 0 to 7 */ |
32 | 32 | #define SOF_RT5682_MCLK_EN BIT(0) |
33 | | -#define SOF_RT5682_MCLK_BYTCHT_EN BIT(1) |
34 | 33 |
|
35 | 34 | /* Default: MCLK on, MCLK 19.2M, SSP0 */ |
36 | 35 | static unsigned long sof_rt5682_quirk = SOF_RT5682_MCLK_EN | |
@@ -206,7 +205,7 @@ static int sof_rt5682_codec_init(struct snd_soc_pcm_runtime *rtd) |
206 | 205 | } |
207 | 206 | } |
208 | 207 |
|
209 | | - if (sof_rt5682_quirk & SOF_RT5682_MCLK_BYTCHT_EN) { |
| 208 | + if (ctx->rt5682.is_legacy_cpu) { |
210 | 209 | /* |
211 | 210 | * The firmware might enable the clock at |
212 | 211 | * boot (this information may or may not |
@@ -279,7 +278,7 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream, |
279 | 278 | int pll_id, pll_source, pll_in, pll_out, clk_id, ret; |
280 | 279 |
|
281 | 280 | if (ctx->rt5682.mclk_en) { |
282 | | - if (sof_rt5682_quirk & SOF_RT5682_MCLK_BYTCHT_EN) { |
| 281 | + if (ctx->rt5682.is_legacy_cpu) { |
283 | 282 | ret = clk_prepare_enable(ctx->rt5682.mclk); |
284 | 283 | if (ret < 0) { |
285 | 284 | dev_err(rtd->dev, |
@@ -661,7 +660,6 @@ static int sof_audio_probe(struct platform_device *pdev) |
661 | 660 |
|
662 | 661 | /* default quirk for legacy cpu */ |
663 | 662 | sof_rt5682_quirk = SOF_RT5682_MCLK_EN | |
664 | | - SOF_RT5682_MCLK_BYTCHT_EN | |
665 | 663 | SOF_SSP_PORT_CODEC(2); |
666 | 664 | } |
667 | 665 |
|
@@ -728,26 +726,27 @@ static int sof_audio_probe(struct platform_device *pdev) |
728 | 726 | } |
729 | 727 | } |
730 | 728 |
|
731 | | - if (sof_rt5682_quirk & SOF_RT5682_MCLK_EN) |
| 729 | + if (sof_rt5682_quirk & SOF_RT5682_MCLK_EN) { |
732 | 730 | ctx->rt5682.mclk_en = true; |
733 | 731 |
|
734 | | - /* need to get main clock from pmc */ |
735 | | - if (sof_rt5682_quirk & SOF_RT5682_MCLK_BYTCHT_EN) { |
736 | | - ctx->rt5682.mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3"); |
737 | | - if (IS_ERR(ctx->rt5682.mclk)) { |
738 | | - ret = PTR_ERR(ctx->rt5682.mclk); |
| 732 | + /* need to get main clock from pmc */ |
| 733 | + if (ctx->rt5682.is_legacy_cpu) { |
| 734 | + ctx->rt5682.mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3"); |
| 735 | + if (IS_ERR(ctx->rt5682.mclk)) { |
| 736 | + ret = PTR_ERR(ctx->rt5682.mclk); |
739 | 737 |
|
740 | | - dev_err(&pdev->dev, |
741 | | - "Failed to get MCLK from pmc_plt_clk_3: %d\n", |
742 | | - ret); |
743 | | - return ret; |
744 | | - } |
| 738 | + dev_err(&pdev->dev, |
| 739 | + "Failed to get MCLK from pmc_plt_clk_3: %d\n", |
| 740 | + ret); |
| 741 | + return ret; |
| 742 | + } |
745 | 743 |
|
746 | | - ret = clk_prepare_enable(ctx->rt5682.mclk); |
747 | | - if (ret < 0) { |
748 | | - dev_err(&pdev->dev, |
749 | | - "could not configure MCLK state"); |
750 | | - return ret; |
| 744 | + ret = clk_prepare_enable(ctx->rt5682.mclk); |
| 745 | + if (ret < 0) { |
| 746 | + dev_err(&pdev->dev, |
| 747 | + "could not configure MCLK state"); |
| 748 | + return ret; |
| 749 | + } |
751 | 750 | } |
752 | 751 | } |
753 | 752 |
|
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