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spi: zynqmp-gqspi: Clean up the driver a bit
Merge series from Sean Anderson <[email protected]>: Here are a few mostly independent cleanups I came up with while writing some other patches. Feel free to apply them in piecemeal if you like.
2 parents c1ac984 + 8978530 commit 26a756f

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+77
-92
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1 file changed

+77
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‎drivers/spi/spi-zynqmp-gqspi.c‎

Lines changed: 77 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,6 @@
8282
#define GQSPI_GENFIFO_RX 0x00020000
8383
#define GQSPI_GENFIFO_STRIPE 0x00040000
8484
#define GQSPI_GENFIFO_POLL 0x00080000
85-
#define GQSPI_GENFIFO_EXP_START 0x00000100
8685
#define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
8786
#define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
8887
#define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
@@ -580,6 +579,8 @@ static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
580579
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
581580
zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
582581
}
582+
583+
dev_dbg(xqspi->dev, "config speed %u\n", req_speed_hz);
583584
return 0;
584585
}
585586

@@ -670,69 +671,77 @@ static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
670671
static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
671672
u32 genfifoentry)
672673
{
673-
u32 transfer_len = 0;
674+
u32 transfer_len, tempcount, exponent;
675+
u8 imm_data;
674676

675-
if (xqspi->txbuf) {
676-
genfifoentry &= ~GQSPI_GENFIFO_RX;
677-
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
678-
genfifoentry |= GQSPI_GENFIFO_TX;
679-
transfer_len = xqspi->bytes_to_transfer;
680-
} else if (xqspi->rxbuf) {
681-
genfifoentry &= ~GQSPI_GENFIFO_TX;
682-
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
677+
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
678+
if (xqspi->rxbuf) {
683679
genfifoentry |= GQSPI_GENFIFO_RX;
684680
if (xqspi->mode == GQSPI_MODE_DMA)
685681
transfer_len = xqspi->dma_rx_bytes;
686682
else
687683
transfer_len = xqspi->bytes_to_receive;
688684
} else {
689-
/* Sending dummy circles here */
690-
genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
691-
genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
692685
transfer_len = xqspi->bytes_to_transfer;
693686
}
687+
688+
if (xqspi->txbuf)
689+
genfifoentry |= GQSPI_GENFIFO_TX;
690+
694691
genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
695692
xqspi->genfifoentry = genfifoentry;
696-
697-
if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
698-
genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
699-
genfifoentry |= transfer_len;
700-
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
701-
} else {
702-
int tempcount = transfer_len;
703-
u32 exponent = 8; /* 2^8 = 256 */
704-
u8 imm_data = tempcount & 0xFF;
705-
706-
tempcount &= ~(tempcount & 0xFF);
707-
/* Immediate entry */
708-
if (tempcount != 0) {
709-
/* Exponent entries */
710-
genfifoentry |= GQSPI_GENFIFO_EXP;
711-
while (tempcount != 0) {
712-
if (tempcount & GQSPI_GENFIFO_EXP_START) {
713-
genfifoentry &=
714-
~GQSPI_GENFIFO_IMM_DATA_MASK;
715-
genfifoentry |= exponent;
716-
zynqmp_gqspi_write(xqspi,
717-
GQSPI_GEN_FIFO_OFST,
718-
genfifoentry);
719-
}
720-
tempcount = tempcount >> 1;
721-
exponent++;
722-
}
723-
}
724-
if (imm_data != 0) {
725-
genfifoentry &= ~GQSPI_GENFIFO_EXP;
726-
genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
727-
genfifoentry |= (u8)(imm_data & 0xFF);
693+
dev_dbg(xqspi->dev, "genfifo %05x transfer_len %u\n",
694+
genfifoentry, transfer_len);
695+
696+
/* Exponent entries */
697+
imm_data = transfer_len;
698+
tempcount = transfer_len >> 8;
699+
exponent = 8;
700+
genfifoentry |= GQSPI_GENFIFO_EXP;
701+
while (tempcount) {
702+
if (tempcount & 1)
728703
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
729-
genfifoentry);
730-
}
731-
}
732-
if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
733-
/* Dummy generic FIFO entry */
734-
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
704+
genfifoentry | exponent);
705+
tempcount >>= 1;
706+
exponent++;
735707
}
708+
709+
/* Immediate entry */
710+
genfifoentry &= ~GQSPI_GENFIFO_EXP;
711+
if (imm_data)
712+
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
713+
genfifoentry | imm_data);
714+
715+
/* Dummy generic FIFO entry */
716+
if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf)
717+
zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0);
718+
}
719+
720+
/**
721+
* zynqmp_qspi_disable_dma() - Disable DMA mode
722+
* @xqspi: GQSPI instance
723+
*/
724+
static void zynqmp_qspi_disable_dma(struct zynqmp_qspi *xqspi)
725+
{
726+
u32 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
727+
728+
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
729+
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
730+
xqspi->mode = GQSPI_MODE_IO;
731+
}
732+
733+
/**
734+
* zynqmp_qspi_enable_dma() - Enable DMA mode
735+
* @xqspi: GQSPI instance
736+
*/
737+
static void zynqmp_qspi_enable_dma(struct zynqmp_qspi *xqspi)
738+
{
739+
u32 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
740+
741+
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
742+
config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
743+
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
744+
xqspi->mode = GQSPI_MODE_DMA;
736745
}
737746

738747
/**
@@ -744,7 +753,7 @@ static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
744753
*/
745754
static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
746755
{
747-
u32 config_reg, genfifoentry;
756+
u32 genfifoentry;
748757

749758
dma_unmap_single(xqspi->dev, xqspi->dma_addr,
750759
xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
@@ -758,9 +767,7 @@ static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
758767

759768
if (xqspi->bytes_to_receive > 0) {
760769
/* Switch to IO mode,for remaining bytes to receive */
761-
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
762-
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
763-
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
770+
zynqmp_qspi_disable_dma(xqspi);
764771

765772
/* Initiate the transfer of remaining bytes */
766773
genfifoentry = xqspi->genfifoentry;
@@ -799,7 +806,6 @@ static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
799806
static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
800807
{
801808
struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
802-
irqreturn_t ret = IRQ_NONE;
803809
u32 status, mask, dma_status = 0;
804810

805811
status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
@@ -814,27 +820,24 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
814820
dma_status);
815821
}
816822

817-
if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
823+
if (!mask && !dma_status)
824+
return IRQ_NONE;
825+
826+
if (mask & GQSPI_ISR_TXNOT_FULL_MASK)
818827
zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
819-
ret = IRQ_HANDLED;
820-
}
821828

822-
if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
829+
if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK)
823830
zynqmp_process_dma_irq(xqspi);
824-
ret = IRQ_HANDLED;
825-
} else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
826-
(mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
831+
else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
832+
(mask & GQSPI_IER_GENFIFOEMPTY_MASK))
827833
zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
828-
ret = IRQ_HANDLED;
829-
}
830834

831835
if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
832836
((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
833837
zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
834838
complete(&xqspi->data_completion);
835-
ret = IRQ_HANDLED;
836839
}
837-
return ret;
840+
return IRQ_HANDLED;
838841
}
839842

840843
/**
@@ -845,17 +848,14 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
845848
*/
846849
static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
847850
{
848-
u32 rx_bytes, rx_rem, config_reg;
851+
u32 rx_bytes, rx_rem;
849852
dma_addr_t addr;
850853
u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
851854

852855
if (xqspi->bytes_to_receive < 8 ||
853856
((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
854857
/* Setting to IO mode */
855-
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
856-
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
857-
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
858-
xqspi->mode = GQSPI_MODE_IO;
858+
zynqmp_qspi_disable_dma(xqspi);
859859
xqspi->dma_rx_bytes = 0;
860860
return 0;
861861
}
@@ -878,14 +878,7 @@ static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
878878
zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
879879
((u32)addr) & 0xfff);
880880

881-
/* Enabling the DMA mode */
882-
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
883-
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
884-
config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
885-
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
886-
887-
/* Switch to DMA mode */
888-
xqspi->mode = GQSPI_MODE_DMA;
881+
zynqmp_qspi_enable_dma(xqspi);
889882

890883
/* Write the number of bytes to transfer */
891884
zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
@@ -905,18 +898,10 @@ static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
905898
static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
906899
u32 genfifoentry)
907900
{
908-
u32 config_reg;
909-
910901
zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
911902
zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
912-
if (xqspi->mode == GQSPI_MODE_DMA) {
913-
config_reg = zynqmp_gqspi_read(xqspi,
914-
GQSPI_CONFIG_OFST);
915-
config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
916-
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
917-
config_reg);
918-
xqspi->mode = GQSPI_MODE_IO;
919-
}
903+
if (xqspi->mode == GQSPI_MODE_DMA)
904+
zynqmp_qspi_disable_dma(xqspi);
920905
}
921906

922907
/**
@@ -1059,8 +1044,8 @@ static unsigned long zynqmp_qspi_timeout(struct zynqmp_qspi *xqspi, u8 bits,
10591044
static int zynqmp_qspi_exec_op(struct spi_mem *mem,
10601045
const struct spi_mem_op *op)
10611046
{
1062-
struct zynqmp_qspi *xqspi = spi_controller_get_devdata
1063-
(mem->spi->controller);
1047+
struct zynqmp_qspi *xqspi =
1048+
spi_controller_get_devdata(mem->spi->controller);
10641049
unsigned long timeout;
10651050
int err = 0, i;
10661051
u32 genfifoentry = 0;

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