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knaerzchemmind
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ARM: dts: rockchip: Fix timer clocks for RK3128
Currently the Rockchip timer source clocks are set to xin24 for no obvious reason and the actual timer clocks (SCLK_TIMER*) will get disabled during boot process as they have no user. That will make the SoC stuck as no timer source exists. Fixes: a0201bf ("ARM: dts: rockchip: add rk3128 soc dtsi") Signed-off-by: Alex Bee <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
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arch/arm/boot/dts/rockchip/rk3128.dtsi

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -234,47 +234,47 @@
234234
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
235235
reg = <0x20044000 0x20>;
236236
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
237-
clocks = <&cru PCLK_TIMER>, <&xin24m>;
237+
clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
238238
clock-names = "pclk", "timer";
239239
};
240240

241241
timer1: timer@20044020 {
242242
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
243243
reg = <0x20044020 0x20>;
244244
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245-
clocks = <&cru PCLK_TIMER>, <&xin24m>;
245+
clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
246246
clock-names = "pclk", "timer";
247247
};
248248

249249
timer2: timer@20044040 {
250250
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
251251
reg = <0x20044040 0x20>;
252252
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
253-
clocks = <&cru PCLK_TIMER>, <&xin24m>;
253+
clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
254254
clock-names = "pclk", "timer";
255255
};
256256

257257
timer3: timer@20044060 {
258258
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
259259
reg = <0x20044060 0x20>;
260260
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
261-
clocks = <&cru PCLK_TIMER>, <&xin24m>;
261+
clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
262262
clock-names = "pclk", "timer";
263263
};
264264

265265
timer4: timer@20044080 {
266266
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
267267
reg = <0x20044080 0x20>;
268268
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
269-
clocks = <&cru PCLK_TIMER>, <&xin24m>;
269+
clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
270270
clock-names = "pclk", "timer";
271271
};
272272

273273
timer5: timer@200440a0 {
274274
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
275275
reg = <0x200440a0 0x20>;
276276
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
277-
clocks = <&cru PCLK_TIMER>, <&xin24m>;
277+
clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
278278
clock-names = "pclk", "timer";
279279
};
280280

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