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Steven LiuLinus Walleij
Steven Liu
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Linus Walleij
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pinctrl: rockchip: add rk3562 support
Add support for the 5 GPIO banks in the rk3562. Signed-off-by: Steven Liu <[email protected]> Signed-off-by: Kever Yang <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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‎drivers/pinctrl/pinctrl-rockchip.c‎

Lines changed: 198 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
33
* Pinctrl driver for Rockchip SoCs
4-
*
4+
* Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
55
* Copyright (c) 2013 MundoReader S.L.
66
* Author: Heiko Stuebner <[email protected]>
77
*
@@ -2003,6 +2003,151 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
20032003
return 0;
20042004
}
20052005

2006+
#define RK3562_DRV_BITS_PER_PIN 8
2007+
#define RK3562_DRV_PINS_PER_REG 2
2008+
#define RK3562_DRV_GPIO0_OFFSET 0x20070
2009+
#define RK3562_DRV_GPIO1_OFFSET 0x200
2010+
#define RK3562_DRV_GPIO2_OFFSET 0x240
2011+
#define RK3562_DRV_GPIO3_OFFSET 0x10280
2012+
#define RK3562_DRV_GPIO4_OFFSET 0x102C0
2013+
2014+
static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2015+
int pin_num, struct regmap **regmap,
2016+
int *reg, u8 *bit)
2017+
{
2018+
struct rockchip_pinctrl *info = bank->drvdata;
2019+
2020+
*regmap = info->regmap_base;
2021+
switch (bank->bank_num) {
2022+
case 0:
2023+
*reg = RK3562_DRV_GPIO0_OFFSET;
2024+
break;
2025+
2026+
case 1:
2027+
*reg = RK3562_DRV_GPIO1_OFFSET;
2028+
break;
2029+
2030+
case 2:
2031+
*reg = RK3562_DRV_GPIO2_OFFSET;
2032+
break;
2033+
2034+
case 3:
2035+
*reg = RK3562_DRV_GPIO3_OFFSET;
2036+
break;
2037+
2038+
case 4:
2039+
*reg = RK3562_DRV_GPIO4_OFFSET;
2040+
break;
2041+
2042+
default:
2043+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2044+
break;
2045+
}
2046+
2047+
*reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
2048+
*bit = pin_num % RK3562_DRV_PINS_PER_REG;
2049+
*bit *= RK3562_DRV_BITS_PER_PIN;
2050+
2051+
return 0;
2052+
}
2053+
2054+
#define RK3562_PULL_BITS_PER_PIN 2
2055+
#define RK3562_PULL_PINS_PER_REG 8
2056+
#define RK3562_PULL_GPIO0_OFFSET 0x20020
2057+
#define RK3562_PULL_GPIO1_OFFSET 0x80
2058+
#define RK3562_PULL_GPIO2_OFFSET 0x90
2059+
#define RK3562_PULL_GPIO3_OFFSET 0x100A0
2060+
#define RK3562_PULL_GPIO4_OFFSET 0x100B0
2061+
2062+
static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2063+
int pin_num, struct regmap **regmap,
2064+
int *reg, u8 *bit)
2065+
{
2066+
struct rockchip_pinctrl *info = bank->drvdata;
2067+
2068+
*regmap = info->regmap_base;
2069+
switch (bank->bank_num) {
2070+
case 0:
2071+
*reg = RK3562_PULL_GPIO0_OFFSET;
2072+
break;
2073+
2074+
case 1:
2075+
*reg = RK3562_PULL_GPIO1_OFFSET;
2076+
break;
2077+
2078+
case 2:
2079+
*reg = RK3562_PULL_GPIO2_OFFSET;
2080+
break;
2081+
2082+
case 3:
2083+
*reg = RK3562_PULL_GPIO3_OFFSET;
2084+
break;
2085+
2086+
case 4:
2087+
*reg = RK3562_PULL_GPIO4_OFFSET;
2088+
break;
2089+
2090+
default:
2091+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2092+
break;
2093+
}
2094+
2095+
*reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
2096+
*bit = pin_num % RK3562_PULL_PINS_PER_REG;
2097+
*bit *= RK3562_PULL_BITS_PER_PIN;
2098+
2099+
return 0;
2100+
}
2101+
2102+
#define RK3562_SMT_BITS_PER_PIN 2
2103+
#define RK3562_SMT_PINS_PER_REG 8
2104+
#define RK3562_SMT_GPIO0_OFFSET 0x20030
2105+
#define RK3562_SMT_GPIO1_OFFSET 0xC0
2106+
#define RK3562_SMT_GPIO2_OFFSET 0xD0
2107+
#define RK3562_SMT_GPIO3_OFFSET 0x100E0
2108+
#define RK3562_SMT_GPIO4_OFFSET 0x100F0
2109+
2110+
static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2111+
int pin_num,
2112+
struct regmap **regmap,
2113+
int *reg, u8 *bit)
2114+
{
2115+
struct rockchip_pinctrl *info = bank->drvdata;
2116+
2117+
*regmap = info->regmap_base;
2118+
switch (bank->bank_num) {
2119+
case 0:
2120+
*reg = RK3562_SMT_GPIO0_OFFSET;
2121+
break;
2122+
2123+
case 1:
2124+
*reg = RK3562_SMT_GPIO1_OFFSET;
2125+
break;
2126+
2127+
case 2:
2128+
*reg = RK3562_SMT_GPIO2_OFFSET;
2129+
break;
2130+
2131+
case 3:
2132+
*reg = RK3562_SMT_GPIO3_OFFSET;
2133+
break;
2134+
2135+
case 4:
2136+
*reg = RK3562_SMT_GPIO4_OFFSET;
2137+
break;
2138+
2139+
default:
2140+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2141+
break;
2142+
}
2143+
2144+
*reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
2145+
*bit = pin_num % RK3562_SMT_PINS_PER_REG;
2146+
*bit *= RK3562_SMT_BITS_PER_PIN;
2147+
2148+
return 0;
2149+
}
2150+
20062151
#define RK3568_PULL_PMU_OFFSET 0x20
20072152
#define RK3568_PULL_GRF_OFFSET 0x80
20082153
#define RK3568_PULL_BITS_PER_PIN 2
@@ -2495,7 +2640,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
24952640
rmask_bits = RK3588_DRV_BITS_PER_PIN;
24962641
ret = strength;
24972642
goto config;
2498-
} else if (ctrl->type == RK3568) {
2643+
} else if (ctrl->type == RK3562 ||
2644+
ctrl->type == RK3568) {
24992645
rmask_bits = RK3568_DRV_BITS_PER_PIN;
25002646
ret = (1 << (strength + 1)) - 1;
25012647
goto config;
@@ -2639,6 +2785,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
26392785
case RK3328:
26402786
case RK3368:
26412787
case RK3399:
2788+
case RK3562:
26422789
case RK3568:
26432790
case RK3576:
26442791
case RK3588:
@@ -2699,6 +2846,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
26992846
case RK3328:
27002847
case RK3368:
27012848
case RK3399:
2849+
case RK3562:
27022850
case RK3568:
27032851
case RK3576:
27042852
case RK3588:
@@ -2810,6 +2958,7 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
28102958

28112959
data >>= bit;
28122960
switch (ctrl->type) {
2961+
case RK3562:
28132962
case RK3568:
28142963
return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
28152964
default:
@@ -2839,6 +2988,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
28392988

28402989
/* enable the write to the equivalent lower bits */
28412990
switch (ctrl->type) {
2991+
case RK3562:
28422992
case RK3568:
28432993
data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
28442994
rmask = data | (data >> 16);
@@ -2965,6 +3115,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
29653115
case RK3328:
29663116
case RK3368:
29673117
case RK3399:
3118+
case RK3562:
29683119
case RK3568:
29693120
case RK3576:
29703121
case RK3588:
@@ -4086,6 +4237,49 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
40864237
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
40874238
};
40884239

4240+
static struct rockchip_pin_bank rk3562_pin_banks[] = {
4241+
PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
4242+
IOMUX_WIDTH_4BIT,
4243+
IOMUX_WIDTH_4BIT,
4244+
IOMUX_WIDTH_4BIT,
4245+
IOMUX_WIDTH_4BIT,
4246+
0x20000, 0x20008, 0x20010, 0x20018),
4247+
PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
4248+
IOMUX_WIDTH_4BIT,
4249+
IOMUX_WIDTH_4BIT,
4250+
IOMUX_WIDTH_4BIT,
4251+
IOMUX_WIDTH_4BIT,
4252+
0, 0x08, 0x10, 0x18),
4253+
PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
4254+
IOMUX_WIDTH_4BIT,
4255+
IOMUX_WIDTH_4BIT,
4256+
IOMUX_WIDTH_4BIT,
4257+
IOMUX_WIDTH_4BIT,
4258+
0x20, 0, 0, 0),
4259+
PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
4260+
IOMUX_WIDTH_4BIT,
4261+
IOMUX_WIDTH_4BIT,
4262+
IOMUX_WIDTH_4BIT,
4263+
IOMUX_WIDTH_4BIT,
4264+
0x10040, 0x10048, 0x10050, 0x10058),
4265+
PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
4266+
IOMUX_WIDTH_4BIT,
4267+
IOMUX_WIDTH_4BIT,
4268+
0,
4269+
0,
4270+
0x10060, 0x10068, 0, 0),
4271+
};
4272+
4273+
static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
4274+
.pin_banks = rk3562_pin_banks,
4275+
.nr_banks = ARRAY_SIZE(rk3562_pin_banks),
4276+
.label = "RK3562-GPIO",
4277+
.type = RK3562,
4278+
.pull_calc_reg = rk3562_calc_pull_reg_and_bit,
4279+
.drv_calc_reg = rk3562_calc_drv_reg_and_bit,
4280+
.schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
4281+
};
4282+
40894283
static struct rockchip_pin_bank rk3568_pin_banks[] = {
40904284
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
40914285
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
@@ -4210,6 +4404,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
42104404
.data = &rk3368_pin_ctrl },
42114405
{ .compatible = "rockchip,rk3399-pinctrl",
42124406
.data = &rk3399_pin_ctrl },
4407+
{ .compatible = "rockchip,rk3562-pinctrl",
4408+
.data = &rk3562_pin_ctrl },
42134409
{ .compatible = "rockchip,rk3568-pinctrl",
42144410
.data = &rk3568_pin_ctrl },
42154411
{ .compatible = "rockchip,rk3576-pinctrl",

‎drivers/pinctrl/pinctrl-rockchip.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* SPDX-License-Identifier: GPL-2.0-only */
22
/*
3-
* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
3+
* Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
44
*
55
* Copyright (c) 2013 MundoReader S.L.
66
* Author: Heiko Stuebner <[email protected]>
@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type {
196196
RK3328,
197197
RK3368,
198198
RK3399,
199+
RK3562,
199200
RK3568,
200201
RK3576,
201202
RK3588,

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