Skip to content

Commit 2f2f5c1

Browse files
devi priyavinodkoul
devi priya
authored and
vinodkoul
committed
phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEs
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm IPQ9574 platform. Reviewed-by: Abel Vesa <[email protected]> Co-developed-by: Anusha Rao <[email protected]> Signed-off-by: Anusha Rao <[email protected]> Signed-off-by: devi priya <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
1 parent 71ae2ac commit 2f2f5c1

File tree

1 file changed

+309
-0
lines changed

1 file changed

+309
-0
lines changed

‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c‎

Lines changed: 309 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -489,6 +489,243 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
489489
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
490490
};
491491

492+
static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = {
493+
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
494+
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
495+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
496+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
497+
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
498+
QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
499+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
500+
QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
501+
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
502+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
503+
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
504+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
505+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
506+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
507+
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
508+
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
509+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
510+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
511+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
512+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
513+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
514+
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
515+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
516+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
517+
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
518+
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
519+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
520+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
521+
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
522+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
523+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
524+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
525+
QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
526+
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
527+
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
528+
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
529+
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
530+
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
531+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
532+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
533+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
534+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
535+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
536+
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
537+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
538+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
539+
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
540+
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
541+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
542+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
543+
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
544+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
545+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
546+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
547+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
548+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
549+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
550+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
551+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
552+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
553+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
554+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
555+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
556+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
557+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
558+
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
559+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
560+
};
561+
562+
static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
563+
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
564+
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
565+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
566+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
567+
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
568+
QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
569+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
570+
QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
571+
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
572+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
573+
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
574+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
575+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
576+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
577+
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
578+
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
579+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
580+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
581+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
582+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
583+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
584+
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
585+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
586+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
587+
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
588+
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
589+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
590+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
591+
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
592+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
593+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
594+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
595+
QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
596+
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
597+
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
598+
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
599+
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
600+
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
601+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
602+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
603+
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
604+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
605+
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
606+
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
607+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
608+
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
609+
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
610+
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
611+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
612+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
613+
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
614+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
615+
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
616+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
617+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
618+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
619+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
620+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
621+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
622+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
623+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
624+
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
625+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
626+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
627+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
628+
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
629+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
630+
};
631+
632+
static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = {
633+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
634+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
635+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
636+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
637+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
638+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
639+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
640+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
641+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
642+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
643+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
644+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73),
645+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80),
646+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
647+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
648+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
649+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
650+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
651+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00),
652+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
653+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
654+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
655+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
656+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
657+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02),
658+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
659+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
660+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
661+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
662+
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
663+
};
664+
665+
static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = {
666+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
667+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
668+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
669+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
670+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
671+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
672+
};
673+
674+
static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = {
675+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
676+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
677+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
678+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
679+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
680+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
681+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14),
682+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10),
683+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b),
684+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
685+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
686+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
687+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
688+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
689+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
690+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
691+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06),
692+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
693+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
694+
};
695+
696+
static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = {
697+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
698+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
699+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
700+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
701+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
702+
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
703+
};
704+
705+
static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
706+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
707+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
708+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
709+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
710+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
711+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
712+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),
713+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),
714+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b),
715+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),
716+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),
717+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
718+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),
719+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
720+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),
721+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
722+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),
723+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a),
724+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),
725+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
726+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
727+
};
728+
492729
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
493730
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
494731
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -2535,6 +2772,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
25352772
.rx2 = 0x1800,
25362773
};
25372774

2775+
static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {
2776+
.serdes = 0,
2777+
.pcs = 0x1000,
2778+
.pcs_misc = 0x1400,
2779+
.tx = 0x0200,
2780+
.rx = 0x0400,
2781+
.tx2 = 0x0600,
2782+
.rx2 = 0x0800,
2783+
};
2784+
25382785
static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
25392786
.serdes = 0x1000,
25402787
.pcs = 0x1200,
@@ -2647,6 +2894,62 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
26472894
.phy_status = PHYSTATUS,
26482895
};
26492896

2897+
static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = {
2898+
.lanes = 1,
2899+
2900+
.offsets = &qmp_pcie_offsets_v4x1,
2901+
2902+
.tbls = {
2903+
.serdes = ipq9574_gen3x1_pcie_serdes_tbl,
2904+
.serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl),
2905+
.tx = ipq8074_pcie_gen3_tx_tbl,
2906+
.tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
2907+
.rx = ipq9574_pcie_rx_tbl,
2908+
.rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
2909+
.pcs = ipq9574_gen3x1_pcie_pcs_tbl,
2910+
.pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl),
2911+
.pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl,
2912+
.pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl),
2913+
},
2914+
.reset_list = ipq8074_pciephy_reset_l,
2915+
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2916+
.vreg_list = NULL,
2917+
.num_vregs = 0,
2918+
.regs = pciephy_v4_regs_layout,
2919+
2920+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2921+
.phy_status = PHYSTATUS,
2922+
.pipe_clock_rate = 250000000,
2923+
};
2924+
2925+
static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = {
2926+
.lanes = 2,
2927+
2928+
.offsets = &qmp_pcie_offsets_ipq9574,
2929+
2930+
.tbls = {
2931+
.serdes = ipq9574_gen3x2_pcie_serdes_tbl,
2932+
.serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
2933+
.tx = ipq8074_pcie_gen3_tx_tbl,
2934+
.tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
2935+
.rx = ipq9574_pcie_rx_tbl,
2936+
.rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
2937+
.pcs = ipq9574_gen3x2_pcie_pcs_tbl,
2938+
.pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl),
2939+
.pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl,
2940+
.pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
2941+
},
2942+
.reset_list = ipq8074_pciephy_reset_l,
2943+
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2944+
.vreg_list = NULL,
2945+
.num_vregs = 0,
2946+
.regs = pciephy_v5_regs_layout,
2947+
2948+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2949+
.phy_status = PHYSTATUS,
2950+
.pipe_clock_rate = 250000000,
2951+
};
2952+
26502953
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
26512954
.lanes = 1,
26522955

@@ -4030,6 +4333,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
40304333
}, {
40314334
.compatible = "qcom,ipq8074-qmp-pcie-phy",
40324335
.data = &ipq8074_pciephy_cfg,
4336+
}, {
4337+
.compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
4338+
.data = &ipq9574_gen3x1_pciephy_cfg,
4339+
}, {
4340+
.compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
4341+
.data = &ipq9574_gen3x2_pciephy_cfg,
40334342
}, {
40344343
.compatible = "qcom,msm8998-qmp-pcie-phy",
40354344
.data = &msm8998_pciephy_cfg,

0 commit comments

Comments
 (0)